ZVP4105A

P-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET ISSUE 2 – MARCH 94 FEATURES * 50 Volt VDS * RDS(on)=10Ω * Low threshold ZVP4105A D G S ABSOLUTE MAXIMUM RATINGS. PARAMETER Drain-Source Voltage Continuous Drain Current at Tamb=25°C Pulsed Drain Current Gate Source Voltage Power Dissipation at Tamb=25°C Operating and Storage Temperature Range SYMBOL VDS ID IDM VGS Ptot Tj:Tstg -50 E-Line TO92 Compatible VALUE -175 -520 ± 20 UNIT V mA mA V mW °C 625 -55 to +150 ELECTRICAL CHARACTERISTICS (at Tamb = 25°C unless otherwise stated). PARAMETER SYMBOL MIN. BVDSS VGS(th) IGSS IDSS -50 -0.8 -2.0 10 -15 -60 -100 10 50 40 15 6 10 10 18 25 MAX. UNIT CONDITIONS. V V nA µA µA Ω Drain-Source Breakdown Voltage Gate-Source Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current ID=-0.25mA, VGS=0V ID=-1mA, VDS= VGS VGS=± 20V, VDS=0V VDS=-50V, VGS=0V VDS=-50V, VGS=0V, T=125°C(2) VDS=-25V, VGS=0V VGS=-5V,ID=-100mA VDS=-25V,ID=-100mA nA Static Drain-Source On-State RDS(on) Resistance (1) Forward Transconductance (1)(2) Input Capacitance (2)(4) Common Source Output Capacitance (2)(4) Reverse Transfer Capacitance (2)(4) Rise Time (2)(3)(4) Fall Time (2)(3)(4) gfs Ciss Coss Crss mS pF pF pF ns ns ns ns VDS=-25V, VGS=0V, f=1MHz Turn-On Delay Time (2)(3)(4) td(on) tr tf Turn-Off Delay Time (2)(3)(4) td(off) VDD ≈ -30V, ID=-270mA (1) Measured under pulsed conditions. Width=300µs. Duty cycle ≤2% (2) Sample test. (3) Switching times measured with 50Ω source impedance and <5ns rise ...