Shift Register. 74LS194A Datasheet

74LS194A Register. Datasheet pdf. Equivalent

74LS194A Datasheet
Recommendation 74LS194A Datasheet
Part 74LS194A
Description 4-Bit Bidirectional Universal Shift Register
Feature 74LS194A; SN74LS194A 4−Bit Bidirectional Universal Shift Register The SN74LS194A is a High Speed 4-Bit Bidire.
Manufacture ON Semiconductor
Datasheet
Download 74LS194A Datasheet




ON Semiconductor 74LS194A
SN74LS194A
4−Bit Bidirectional
Universal Shift Register
The SN74LS194A is a High Speed 4-Bit Bidirectional Universal
Shift Register. As a high speed multifunctional sequential building
block, it is useful in a wide variety of applications. It may be used in
serial-serial, shift left, shift right, serial-parallel, parallel-serial, and
parallel-parallel data register transfers. The LS194A is similar in
operation to the LS195A Universal Shift Register, with added features
of shift left without external connections and hold (do nothing) modes
of operation. It utilizes the Schottky diode clamped process to achieve
high speeds and is fully compatible with all ON Semiconductor TTL
families.
Typical Shift Frequency of 36 MHz
Asynchronous Master Reset
Hold (Do Nothing) Mode
Fully Synchronous Serial or Parallel Data Transfers
Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min Typ Max Unit
VCC
Supply Voltage
TA
Operating Ambient
Temperature Range
4.75 5.0 5.25
V
0
25
70
°C
IOH
Output Current High
IOL
Output Current Low
0.4 mA
8.0
mA
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LOW
POWER
SCHOTTKY
16
1
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device
Package
Shipping
SN74LS194AN 16 Pin DIP 2000 Units/Box
SN74LS194AD
SOIC16 38 Units/Rail
SN74LS194ADR2 SOIC16 2500/Tape & Reel
© Semiconductor Components Industries, LLC, 2006
1
July, 2006 Rev. 8
Publication Order Number:
SN74LS194A/D



ON Semiconductor 74LS194A
SN74LS194A
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC Q0 Q1 Q2 Q3 CP S1 S0
16 15 14 13 12 11 10 9
1 2 3 4 56 78
MR DSR P0 P1 P2 P3 DSL GND
PIN NAMES
S0, S1
P0 − P3
DSR
DSL
CP
MR
Q0 − Q3
Mode Control Inputs
Parallel Data Inputs
Serial (Shift Right) Data Input
Serial (Shift Left) Data Input
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Parallel Outputs
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
LOADING (Note a)
HIGH
LOW
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
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ON Semiconductor 74LS194A
P0
10
3
S1
9
S0
2
DSR
SN74LS194A
LOGIC DIAGRAM
P1
P2
4
5
P3
6
7
DSL
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
11
CP
1
MR
S Q0
CP
R
CLEAR
15
Q0
S Q1
CP
R
CLEAR
14
Q1
S Q2
CP
R
CLEAR
13
Q2
S Q3
CP
R
CLEAR
12
Q3
FUNCTIONAL DESCRIPTION
The Logic Diagram and Truth Table indicate the
functional characteristics of the LS194A 4-Bit Bidirectional
Shift Register. The LS194A is similar in operation to the
ON Semiconductor LS195A Universal Shift Register when
used in serial or parallel data register transfers. Some of the
common features of the two devices are described below:
All data and mode control inputs are edge-triggered,
responding only to the LOW to HIGH transition of the Clock
(CP). The only timing restriction, therefore, is that the mode
control and selected data inputs must be stable one set-up
time prior to the positive transition of the clock pulse.
The register is fully synchronous, with all operations
taking place in less than 15 ns (typical) making the device
especially useful for implementing very high speed CPUs,
or the memory buffer registers.
The four parallel data inputs (P0, P1, P2, P3) are D-type
inputs. When both S0 and S1 are HIGH, the data appearing
on P0, P1, P2, and P3 inputs is transferred to the Q0, Q1, Q2,
and Q3 outputs respectively following the next LOW to
HIGH transition of the clock.
The asynchronous Master Reset (MR), when LOW,
overrides all other input conditions and forces the Q outputs
LOW.
Special logic features of the LS194A design which
increase the range of application are described below:
Two mode control inputs (S0, S1) determine the
synchronous operation of the device. As shown in the Mode
Selection Table, data can be entered and shifted from left to
right (shift right, Q0 ! Q1, etc.) or right to left (shift left, Q3
! Q2, etc.), or parallel data can be entered loading all four
bits of the register simultaneously. When both S0 and S1,are
LOW, the existing data is retained in a “do nothing” mode
without restricting the HIGH to LOW clock transition.
D-type serial data inputs (DSR, DSL) are provided on both
the first and last stages to allow multistage shift right or shift
left data transfers without interfering with parallel load
operation.
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