DatasheetsPDF.com

IDT74FCT2543T Dataheets PDF



Part Number IDT74FCT2543T
Manufacturers Integrated Device Tech
Logo Integrated Device Tech
Description FAST CMOS OCTAL LATCHED TRANSCEIVER
Datasheet IDT74FCT2543T DatasheetIDT74FCT2543T Datasheet (PDF)

FAST CMOS OCTAL LATCHED TRANSCEIVER Integrated Device Technology, Inc. IDT54/74FCT543T/AT/CT/DT IDT54/74FCT2543T/AT/CT FEATURES: • Common features: – Low input and output leakage ≤1µA (max.) – CMOS power levels – True TTL input and output compatibility – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) – Meets or exceeds JEDEC standard 18 specifications – Product available in Radiation Tolerant and Radiation Enhanced versions – Military product compliant to MIL-STD-883, Class B and DESC listed (dual mark.

  IDT74FCT2543T   IDT74FCT2543T



Document
FAST CMOS OCTAL LATCHED TRANSCEIVER Integrated Device Technology, Inc. IDT54/74FCT543T/AT/CT/DT IDT54/74FCT2543T/AT/CT FEATURES: • Common features: – Low input and output leakage ≤1µA (max.) – CMOS power levels – True TTL input and output compatibility – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) – Meets or exceeds JEDEC standard 18 specifications – Product available in Radiation Tolerant and Radiation Enhanced versions – Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) – Available in DIP, SOIC, SSOP, QSOP, CERPACK and LCC packages • Features for FCT543T: – Std., A, C and D speed grades – High drive outputs (-15mA IOH, 64mA IOL) – Power off disable outputs permit “live insertion” • Features for FCT2543T: – Std., A, and C speed grades – Resistor outputs (-15mA IOH, 12mA IOL Com.) (-12mA IOH, 12mA IOL Mil.) – Reduced system switching noise DESCRIPTION: The FCT543T/FCT2543T is a non-inverting octal transceiver built using an advanced dual metal CMOS technology. This device contains two sets of eight D-type latches with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable (CEAB) input must be LOW in order to enter data from A0–A7 or to take data from B0–B7, as indicated in the Function Table. With CEAB LOW, a LOW signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the 3-state B output buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar, but uses the CEBA, LEBA and OEBA inputs. The FCT2543T has balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot and controlled output fall times-reducing the need for external series terminating resistors. FCT2xxxT parts are plug-in replacements for FCTxxxT parts. FUNCTIONAL BLOCK DIAGRAM DETAIL A D LE A0 Q D LE Q B0 A1 A2 A3 A4 A5 A6 A7 DETAIL A x 7 B1 B2 B3 B4 B5 B6 B7 OEBA OEAB CEBA LEBA The IDT logo is a registered trademark of Integrated Device Technology, Inc. CEAB 2613 drw 01 LEAB MILITARY AND COMMERCIAL TEMPERATURE RANGES ©1995 Integrated Device Technology, Inc. JANUARY 1995 DSC-4203/5 6.17 1 IDT54/74FCT543T/AT/CT/DT - 2543T/AT/CT FAST CMOS OCTAL LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES INDEX 11 12 14 13 2613 drw 02 A7 CEAB GND NC OEAB LEAB B7 LEBA OEBA A0 A1 A2 A3 A4 A5 A6 A7 CEAB GND 1 2 3 4 5 6 7 8 9 10 24 23 22 P24-1 D24-1 SO24-2 SO24-7 SO24-8 & E24-1 21 20 19 18 17 16 15 Vcc CEBA B0 B1 B2 B3 B4 B5 B6 B7 LEAB OEAB A0 OEBA LEBA NC Vcc CEBA B0 4 3 2 1 28 27 26 25 24 23 22 21 20 5 6 7 8 9 10 PIN CONFIGURATIONS A1 A2 A3 NC A4 A5 A6 L28-1 11 19 12 13 14 15 16 17 18 B1 B2 B3 NC B4 B5 B6 2613 drw 03 DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW LCC TOP VIEW PIN DESCRIPTION Pin Names Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Enable Input (Active LOW) B-to-A Enable Input (Active LOW) A-to-B Latch Enable Input (Active LOW) B-to-A Latch Enable Input (Active LOW) A-to-B Data Inputs or B-to-A 3-State Outputs B-to-A Data Inputs or A-to-B 3-State Outputs 2613 tbl 01 FUNCTION TABLE(1, 2) For A-to-B (Symmetric with B-to-A) Inputs Latch Status Output Buffers B0–B7 High Z — High Z Current A Inputs Previous* A Inputs OEAB OEBA CEAB CEBA LEAB LEBA A0–A7 B0–B7 CEAB H — — L L LEAB — H — L H OEAB — — H L L A-to-B Storing Storing — Transparent Storing ABSOLUTE MAXIMUM RATINGS Symbol Rating Commercial VTERM(2) Terminal Voltage –0.5 to +7.0 with Respect to GND VTERM(3) Terminal Voltage –0.5 to with Respect to VCC +0.5 GND TA Operating 0 to +70 Temperature TBIAS Temperature –55 to +125 Under Bias TSTG Storage –55 to +125 Temperature PT Power Dissipation 0.5 I OUT DC Output Current –60 to +120 (1) Military –0.5 to +7.0 Unit V NOTES: 2613 tbl 02 1. * Before LEAB LOW-to-HIGH Transition H = HIGH Voltage Level L = LOW Voltage Level — = Don’t Care or Irrelevant 2. A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA and OEBA. –0.5 to VCC +0.5 –55 to +125 –65 to +135 –65 to +150 0.5 –60 to +120 V °C °C °C W mA CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. Unit 10 pF 12 pF 2613 lnk 04 NOTE: 1. This parameter is measured at characterization but not tested. 2613 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability..


IDT74FCT2541T IDT74FCT2543T IDT74FCT2573T


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)