Document
®
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
DESCRIPTION:
IDT54/74FCT299 IDT54/74FCT299A IDT54/74FCT299C
Integrated Device Technology, Inc.
FEATURES:
• • • • • • • • • • • • • • IDT54/74FCT299 equivalent to FAST™ speed IDT54/74FCT299A 25% faster than FAST IDT54/74FCT299C 35% faster than FAST Equivalent to FAST output drive over full temperature and voltage supply extremes IOL = 48mA (commercial) and 32mA (military) CMOS power levels (1mW typ. static) TTL input and output level compatible CMOS output level compatible Substantially lower input current levels than FAST (5µA max.) 8-input universal shift register JEDEC standard pinout for DIP and LCC Product available in Radiation Tolerant and Radiation Enhanced versions Military product compliant to MIL-STD-883, Class B Standard Military Drawing# 5962-86862 is listed on this function. Refer to section 2.
The IDT54/74FCT299 and IDT54/74FCT299A/C are built using an advanced dual metal CMOS technology. The IDT54/ 74FCT299 and IDT54/74FCT299A/C are 8-input universal shift/storage registers with 3-state outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs are provided for flip-flops Q0 and Q7 to allow easy serial cascading. A separate active LOW Master Reset is used to reset the register.
FUNCTIONAL BLOCK DIAGRAM
S1 S0
DS 7 DS 0
CP CD Q0 MR OE 1 OE 2 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
2561 drw 01
D CP Q
CD
D CP Q
CD
D CP Q
CD
D CP Q
CD
D CP Q
CD
D CP Q
CD
D CP Q
CD
D CP Q Q7
The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a registered trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1994 Integrated Device Technology, Inc.
MAY 1992
DSC-4604/3
7.11
1
IDT54/74FCT299/A/C FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INDEX
S0 OE 1 OE 2 I/O 6 I/O 4 I/O 2 I/O 0 Q0 MR GND
1 2 3 4 5 6 7 8 9 10
20 19
P20-1 D20-1 S020-2 & E20-1
18 17 16 15 14 13 12 11
Vcc S1 DS 7 Q7 I/O 7 I/O 5 I/O 3 I/O 1 CP DS 0
I/O 6 I/O 4 I/O 2 I/O 0 Q0
OE 2 OE 1 S0 Vcc S1
3 2 4 5 6 7 8 1 20 19 18 17 16 15 14 9 10 11 12 13
PIN CONFIGURATIONS
L20-2
DS 7 Q7 I/O 7 I/O 5 I/O 3
DIP/SOIC/CERPACK TOP VIEW
MR GND DS0 CP I/O 1
LCC TOP VIEW
2561 drw 02
PIN DESCRIPTION
Pin Names CP DS0 DS7 S0, S1 Description Clock Pulse Input (Active Edge Rising) Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Asynchronous Master Reset Input (Active LOW) 3-State Output Enable Inputs (Active LOW) Parallel Data Inputs or 3-State Parallel Outputs Serial Outputs
2561 tbl 01
FUNCTION TABLE(1)
Inputs
MR S1
L H H H H X H L H L
S0 X H H L L
CP X ↑ ↑ ↑ X
Response Asynchronous Reset Q0–Q7 = LOW Parallel Load; I/On → Qn Shift Right; DS0 → Q0, Q0 → Q1, etc. Shift Left; DS7 → Q7, Q7→ Q6, etc. Hold
2561 tbl.