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74HCT297 Dataheets PDF



Part Number 74HCT297
Manufacturers Philips
Logo Philips
Description Digital phase-locked-loop filter
Datasheet 74HCT297 Datasheet74HCT297 Datasheet (PDF)

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT297 Digital phase-locked-loop filter Product specification File under Integrated Circuits, IC06 September 1993 Philips Semiconductors Product specification Digital phase-locked-loop filter FEATURES • Digital design avoids analog compensation e.

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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT297 Digital phase-locked-loop filter Product specification File under Integrated Circuits, IC06 September 1993 Philips Semiconductors Product specification Digital phase-locked-loop filter FEATURES • Digital design avoids analog compensation errors • Easily cascadable for higher order loops • Useful frequency range: – DC to 55 MHz typical (K-clock) – DC to 35 MHz typical (I/D-clock) • Dynamically variable bandwidth • Very narrow bandwidth attainable • Power-on reset • Output capability: standard/bus driver • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT297 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT297 are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. These devices contain all the necessary circuits, with the exception of the divide-by-n counter, to build first order phase-locked-loops. Both EXCLUSIVE-OR (XORPD) and edge-controlled (ECPD) phase detectors are provided for maximum flexibility. The input signals for the EXCLUSIVE-OR phase detector must have a 50% duty factor to obtain the maximum lock-range. Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation (see Fig.7) or to cascade to higher order phase-locked-loops. The length of the up/down K-counter is digitally programmable according to the K-counter function table. With, A, B, C and D all LOW, the K-counter is disabled. With A HIGH and B, C and D LOW, the K-counter is only three stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B, C and D are all programmed HIGH, the K-counter becomes seventeen stages long, which narrows the bandwidth or capture range and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A to D inputs can maximize the overall performance of the digital phase-locked loop. The “297” can perform the classic first-order phase-locked-loop function without using analog September 1993 2 74HC/HCT297 components. The accuracy of the digital phase-locked-loop (DPLL) is not affected by VCC and temperature variations but depends solely on accuracies of the K-clock, I/D-clock and loop propagation delays. The phase detector generates an error signal waveform that, at zero phase error, is a 50% duty factor square wave. At the limits of linear operation, the phase detector output will be either HIGH or LOW all of the time depending on the direction of the phase error (φIN − φOUT). Within these limits the phase detector output varies linearly with t.


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