74HCT4015

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4015 Dual 4-bit serial-in/parallel-out shift register Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Dual 4-bit serial-in/parallel-out shift register Product specification 74HC/HCT4015 FEATURES Output capability: standard ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4015 are high-speed Si-gate CMOS devices and are pin compatible with the “4015” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4015 are dual edge-triggered 4-bit static shift registers (serial-to-parallel converters). Each shift register has a serial data input (1D and 2D), a clock input (1CP and 2CP), four fully buffered parallel outputs (1Q0 to 1Q3 and 2Q0 to 2Q3) and an overriding asynchronous master reset (1MR and 2MR). Information present on nD is shifted to the first register position, and all data in the register is shifted one position to the right on the LOW-to-HIGH transition of nCP. A HIGH on nMR clears the register and forces nQ0 to nQ3 to LOW, independent of nCP and nD. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns SYMBOL tPHL/ tPLH fmax CI CPD PARAMETER CONDITIONS TYPICAL HC HCT propagation delay nCP to nQn maximum cloc...