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74HCT4518 Dataheets PDF



Part Number 74HCT4518
Manufacturers Philips
Logo Philips
Description Dual synchronous BCD counter
Datasheet 74HCT4518 Datasheet74HCT4518 Datasheet (PDF)

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4518 Dual synchronous BCD counter Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Dual synchronous BCD counter Product specification 74HC/HCT4518 FEATURES • Output capability: standard • ICC ca.

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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4518 Dual synchronous BCD counter Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Dual synchronous BCD counter Product specification 74HC/HCT4518 FEATURES • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4518 are high-speed Si-gate CMOS devices and are pin compatible with the “4518” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4518 are dual 4-bit internally synchronous BCD counters with an active HIGH clock input (nCP0) and an active LOW clock input (nCP1), buffered outputs from all four bit positions (nQ0 to nQ3) and an active HIGH overriding asynchronous master reset input (nMR). The counter advances on either the LOW-to-HIGH transition of nCP0 if nCP1 is HIGH or the HIGH-to-LOW transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on nMR resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1. APPLICATIONS • Multistage synchronous counting • Multistage asynchronous counting • Frequency dividers QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns SYMBOL PARAMETER CONDITIONS TYPICAL HC HCT tPHL/ tPLH tPHL fmax CI CPD propagation delay nCP0, nCP1 to nQn propagation delay nMR to nQn maximum clock frequency input capacitance power dissipation capacitance per counter CL = 15 pF; VCC = 5 V notes 1 and 2 20 13 61 3.5 29 24 14 55 3.5 27 UNIT ns ns MHz pF pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 2 Philips Semiconductors Dual synchronous BCD counter Product specification 74HC/HCT4518 PIN DESCRIPTION PIN NO. 1, 9 2, 10 3, 4, 5, 6 7, 15 8 11, 12, 13, 14 16 SYMBOL 1CP0, 2CP0 1CP1, 2CP1 1Q0 to 1Q3 1MR, 2MR GND 2Q0 to 2Q3 VCC NAME AND FUNCTION clock inputs (LOW-to-HIGH, edge-triggered) clock inputs (HIGH-to-LOW, edge-triggered) data outputs asynchronous master reset inputs (active HIGH) ground (0 V) data outputs positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Dual synchronous BCD counter Fig.4 Functional diagram. Product specification 74HC/HCT4518 FUNCTION TABLE nCP0 ↑ L ↓ X ↑ H X nCP1 H ↓ X ↑ L ↓ X MR MODE L counter .


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