74HCT73

74HC73 Dual JK flip-flop with reset; negative-edge trigger Rev. 03 — 12 November 2004 Product data sheet 1. General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. The 74HC is a dual negative-edge triggered JK flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. 2. Features s Low-power dissipation s Complies with JEDEC standard no. 7A s ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. s Multiple package options s Specified from −40 °C to +80 °C and from −40 °C to +125 °C. Philips Semiconductors 74HC73 Dual JK flip-flop with reset; negative-edge trigger 3. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. Symbol tPHL, tPLH Parameter propagation delay nCP to nQ nCP to nQ nR to nQ, nQ fmax CI CPD [1] Conditions CL = 15 pF; VCC = 5 V Min - Typ 16 16 15 77 3.5 30 Max - Unit ns ns ns MHz pF pF maximum clock frequency input capac...