74LS153 Selectors/Multiplexers Datasheet

74LS153 Datasheet, PDF, Equivalent


Part Number

74LS153

Description

Dual 1-of-4 Line Data Selectors/Multiplexers

Manufacture

Fairchild Semiconductor

Total Page 5 Pages
Datasheet
Download 74LS153 Datasheet


74LS153
August 1986
Revised March 2000
DM74LS153
Dual 1-of-4 Line Data Selectors/Multiplexers
General Description
Each of these data selectors/multiplexers contains invert-
ers and drivers to supply fully complementary, on-chip,
binary decoding data selection to the AND-OR-invert
gates. Separate strobe inputs are provided for each of the
two four-line sections.
Features
s Permits multiplexing from N lines to 1 line
s Performs at parallel-to-serial conversion
s Strobe (enable) line provided for cascading
(N lines to n lines)
s High fan-out, low impedance, totem pole outputs
s Typical average propagation delay times
From data 14 ns
From strobe 19 ns
From select 22 ns
s Typical power dissipation 31 mW
Ordering Code:
Order Number Package Number
Package Description
DM74LS153M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS153N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Select
Inputs
Data Inputs
Strobe
B A C0 C1 C2 C3
G
XX X X X X
H
LL L X X X
L
LL H X X X
L
LH X L X X
L
LH X H X X
L
HL X X L X
L
HL X X H X
L
HH X X X L
L
HH X X X H
L
Select inputs A and B are common to both sections.
H = HIGH Level
L = LOW Level
X = Don't Care
Output
Y
L
L
H
L
H
L
H
L
H
© 2000 Fairchild Semiconductor Corporation DS006393
www.fairchildsemi.com

74LS153
Logic Diagram
www.fairchildsemi.com
2


Features DM74LS153 Dual 1-of-4 Line Data Selector s/Multiplexers August 1986 Revised Mar ch 2000 DM74LS153 Dual 1-of-4 Line Dat a Selectors/Multiplexers General Descri ption Each of these data selectors/mult iplexers contains inverters and drivers to supply fully complementary, on-chip , binary decoding data selection to the AND-OR-invert gates. Separate strobe i nputs are provided for each of the two four-line sections. Features s Permits multiplexing from N lines to 1 line s Performs at parallel-to-serial conversi on s Strobe (enable) line provided for cascading (N lines to n lines) s High f an-out, low impedance, totem pole outpu ts s Typical average propagation delay times From data From strobe From select 14 ns 19 ns 22 ns s Typical power dis sipation 31 mW Ordering Code: Order Nu mber DM74LS153M DM74LS153N Package Numb er M16A N16E Package Description 16-Lea d Small Outline Integrated Circuit (SOI C), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide .
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