74LS154 Decoder/Demultiplexer Datasheet

74LS154 Datasheet, PDF, Equivalent


Part Number

74LS154

Description

4-Line to 16-Line Decoder/Demultiplexer

Manufacture

Fairchild Semiconductor

Total Page 5 Pages
Datasheet
Download 74LS154 Datasheet


74LS154
August 1986
Revised March 2000
DM74LS154
4-Line to 16-Line Decoder/Demultiplexer
General Description
Each of these 4-line-to-16-line decoders utilizes TTL cir-
cuitry to decode four binary-coded inputs into one of six-
teen mutually exclusive outputs when both the strobe
inputs, G1 and G2, are LOW. The demultiplexing function
is performed by using the 4 input lines to address the out-
put line, passing data from one of the strobe inputs with the
other strobe input LOW. When either strobe input is HIGH,
all outputs are HIGH. These demultiplexers are ideally
suited for implementing high-performance memory decod-
ers. All inputs are buffered and input clamping diodes are
provided to minimize transmission-line effects and thereby
simplify system design.
Features
s Decodes 4 binary-coded inputs into one of 16 mutually
exclusive outputs
s Performs the demultiplexing function by distributing data
from one input line to any one of 16 outputs
s Input clamping diodes simplify system design
s High fan-out, low-impedance, totem-pole outputs
s Typical propagation delay
3 levels of logic 23 ns
Strobe
19 ns
s Typical power dissipation 45 mW
Ordering Code:
Order Number Package Number
Package Description
DM74LS154WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74LS154N
N24A
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Logic Diagram
© 2000 Fairchild Semiconductor Corporation DS006394
www.fairchildsemi.com

74LS154
Function Table
Inputs
Outputs
G1 G2 D C B A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
L L L L L L LHHHHHHHHH H H H H H H
L L L L LHHLHHHHHHHH H H H H H H
L L L LHLHHLHHHHHHH H H H H H H
L L L LHHHHH LHHHHHH H H H H H H
L L LHL LHHHHLHHHHH H H H H H H
L L LHLHHHHHHLHHHH H H H H H H
L L LHHLHHHHHH LHHH H H H H H H
L L LHHHHHHHHHHLHH H H H H H H
L L H L L LHHHHHHHHLH H H H H H H
L L H L LHHHHHHHHHH L H H H H H H
L L H LHLHHHHHHHHHH L H H H H H
L L H LHHHHHHHHHHHH H L H H H H
L L HHL LHHHHHHHHHH H H L H H H
L L HHLHHHHHHHHHHH H H H L H H
L L HHHLHHHHHHHHHH H H H H L H
L L HHHHHHHHHHHHHH H H H H H L
L H XXXXHHHHHHHHHH H H H H H H
H L XXXXHHHHHHHHHH H H H H H H
H H XXXXHHHHHHHHHH H H H H H H
H = HIGH Level
L = Low Level
X = Don’t Care
www.fairchildsemi.com
2


Features DM74LS154 4-Line to 16-Line Decoder/Demu ltiplexer August 1986 Revised March 20 00 DM74LS154 4-Line to 16-Line Decoder /Demultiplexer General Description Each of these 4-line-to-16-line decoders ut ilizes TTL circuitry to decode four bin ary-coded inputs into one of sixteen mu tually exclusive outputs when both the strobe inputs, G1 and G2, are LOW. The demultiplexing function is performed by using the 4 input lines to address the output line, passing data from one of the strobe inputs with the other strobe input LOW. When either strobe input is HIGH, all outputs are HIGH. These demu ltiplexers are ideally suited for imple menting high-performance memory decoder s. All inputs are buffered and input cl amping diodes are provided to minimize transmission-line effects and thereby s implify system design. Features s Deco des 4 binary-coded inputs into one of 1 6 mutually exclusive outputs s Performs the demultiplexing function by distrib uting data from one input line to any one of 16 outputs s Input.
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