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74LS195 Dataheets PDF



Part Number 74LS195
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description LOW POWER SCHOTTKY
Datasheet 74LS195 Datasheet74LS195 Datasheet (PDF)

SN74LS195A Universal 4-Bit Shift Register The SN74LS195A is a high speed 4-Bit Shift Register offering typical shift frequencies of 39 MHz. It is useful for a wide variety of register and counting applications. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all ON Semiconductor TTL products. http://onsemi.com • • • • • Typical Shift Right Frequency of 39 MHz Asynchronous Master Reset J, K Inputs to First Stage Fully Synchronous Serial or Para.

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SN74LS195A Universal 4-Bit Shift Register The SN74LS195A is a high speed 4-Bit Shift Register offering typical shift frequencies of 39 MHz. It is useful for a wide variety of register and counting applications. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all ON Semiconductor TTL products. http://onsemi.com • • • • • Typical Shift Right Frequency of 39 MHz Asynchronous Master Reset J, K Inputs to First Stage Fully Synchronous Serial or Parallel Data Transfers Input Clamp Diodes Limit High Speed Termination Effects LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.75 0 Typ 5.0 25 Max 5.25 70 – 0.4 8.0 Unit V °C mA mA 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS195AN SN74LS195AD Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries, LLC, 1999 1 December, 1999 – Rev. 6 Publication Order Number: SN74LS195A/D SN74LS195A CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Q0 15 Q1 14 Q2 13 Q3 12 Q3 11 CP 10 PE 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 MR 2 J 3 K 4 P0 5 P1 6 P2 7 P3 8 GND LOADING (Note a) PIN NAMES PE P0 – P3 J K CP MR Q0 – Q3 Q3 Parallel Enable (Active LOW) Input Parallel Data Inputs First Stage J (Active HIGH) Input First Stage K (Active LOW) Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Parallel Outputs Complementary Last Stage Output HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L. 5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. LOGIC SYMBOL 9 4 5 6 7 2 10 3 J K PE P0 P1 P2 P3 Q3 11 CP MR Q0 Q1 Q2 Q3 1 15 14 13 12 VCC = PIN 16 GND = PIN 8 http://onsemi.com 2 SN74LS195A LOGIC DIAGRAM PE J 9 2 3 K 4 P0 5 P1 6 P2 7 P3 1 MR 10 CP R CD Q0 CP S VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Q0 15 R CD CP S Q0 14 R CD CP S Q2 13 R CD Q3 CP S Q3 12 11 Q0 Q1 Q2 Q3 Q3 FUNCTIONAL DESCRIPTION The Logic Diagram and Truth Table indicate the functional characteristics of the LS195A 4-Bit Shift Register. The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. The LS195A has two primary modes of operation, shift right (Q0 Q1) and parallel load which are controlled by the state of the Parallel Enable (PE) input. When the PE input is HIGH, serial data enters the first flip-flop Q0 via the J and K inputs and is shifted one bit in the direction Q0 Q1 Q2 Q3 following each LOW to HIGH clock transition. The JK inputs provide the flexibility of the JK type input for special applications, and the simple D type input for general applications by tying the two pins together. When the PE ³ ³ ³ ³ input is LOW, the LS195A appears as four common clocked D flip-flops. The data on the parallel inputs P0, P1, P2, P3 is transferred to the respective Q0, Q1, Q2, Q3 outputs following the LOW to HIGH clock transition. Shift left operations (Q3 Q2) can be achieved by tying the Qn Outputs to the Pn–1 inputs and holding the PE input LOW. All serial and parallel data transfers are synchronous, occurring after each LOW to HIGH clock transition. Since the LS195A utilizes edge-triggering, there is no restriction on the activity of the J, K, Pn and PE inputs for logic operation — except for the set-up and release time requirements. A LOW on the asynchronous Master Reset (MR) input sets all Q outputs LOW, independent of any other input condition. ³ MODE SELECT — TRUTH TABLE INPUTS OPERATING MODES MR Asynchronous Reset Shift, Set First Stage Shift, Reset First Shift, Toggle First Stage Shift, Retain First Stage Parallel Load L H H H H H PE X h h h h I J X h I h I X K X h I I h X Pn X X X X X pn Q0 L H L q0 q0 p0 Q1 L q0 q0 q0 q0 p1 Q2 L q1 q1 q1 q1 p2 Q3 L q2 q2 q2 q2 p3 Q3 H q2 q2 q2 q2 p3 OUTPUTS L = LOW voltage levels H = HIGH voltage levels X = Don’t Care I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition. h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition. pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition. http://onsemi.com 3 SN74LS195A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.7 – 0.65 3.5 0.25 VOL O Output LOW Voltage 0.35 IIH IIL IOS ICC Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.4 – 100 21 0.5 20 V µA mA mA mA mA IOL .


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