74LS251 Selector/Multiplexer Datasheet

74LS251 Datasheet, PDF, Equivalent


Part Number

74LS251

Description

3-STATE 1-of-8 Line Data Selector/Multiplexer

Manufacture

Fairchild Semiconductor

Total Page 6 Pages
Datasheet
Download 74LS251 Datasheet


74LS251
August 1986
Revised March 2000
DM74LS251
3-STATE 1-of-8 Line Data Selector/Multiplexer
General Description
These data selectors/multiplexers contain full on-chip
binary decoding to select one-of-eight data sources, and
feature a strobe-controlled 3-STATE output. The strobe
must be at a low logic level to enable these devices. The 3-
STATE outputs permit direct connection to a common bus.
When the strobe input is HIGH, both outputs are in a high-
impedance state in which both the upper and lower transis-
tors of each totem-pole output are OFF, and the output nei-
ther drives nor loads the bus significantly. When the strobe
is LOW, the outputs are activated and operate as standard
TTL totem-pole outputs.
To minimize the possibility that two outputs will attempt to
take a common bus to opposite logic levels, the output con-
trol circuitry is designed so that the average output disable
time is shorter than the average output enable time.
Features
s 3-STATE version of DM74LS151
s Interface directly with system bus
s Perform parallel-to-serial conversion
s Permit multiplexing from N-lines to one line
s Complementary outputs provide true and inverted data
s Maximum number of common outputs: 129
s Typical propagation delay time (D to Y): 17 ns
s Typical power dissipation: 35 mW
Ordering Code:
Order Number Package Number
Package Description
DM74LS251M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS251N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Select
Strobe
CBA
S
XXX
H
LLL
L
L LH
L
LHL
L
L HH
L
HLL
L
HLH
L
HHL
L
HHH
L
H = HIGH Logic Level
L = LOW Logic Level
X = Don't Care
Z = High Impedance (OFF)
D0, D1…D7 = The level of the respective D input
Outputs
YW
ZZ
D0 D0
D1 D1
D2 D2
D3 D3
D4 D4
D5 D5
D6 D6
D7 D7
© 2000 Fairchild Semiconductor Corporation DS006415
www.fairchildsemi.com

74LS251
Logic Diagram
www.fairchildsemi.com
2


Features DM74LS251 3-STATE 1-of-8 Line Data Selec tor/Multiplexer August 1986 Revised Ma rch 2000 DM74LS251 3-STATE 1-of-8 Line Data Selector/Multiplexer General Desc ription These data selectors/multiplexe rs contain full on-chip binary decoding to select one-of-eight data sources, a nd feature a strobe-controlled 3-STATE output. The strobe must be at a low log ic level to enable these devices. The 3 STATE outputs permit direct connection to a common bus. When the strobe input is HIGH, both outputs are in a highimpe dance state in which both the upper and lower transistors of each totem-pole o utput are OFF, and the output neither d rives nor loads the bus significantly. When the strobe is LOW, the outputs are activated and operate as standard TTL totem-pole outputs. To minimize the pos sibility that two outputs will attempt to take a common bus to opposite logic levels, the output control circuitry is designed so that the average output di sable time is shorter than the average output enable time. Fea.
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