74LS73 Flip-Flops Datasheet
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops
|Total Page||5 Pages|
Revised March 2000
Dual Negative-Edge-Triggered Master-Slave
J-K Flip-Flops with Clear and Complementary Outputs
This device contains two independent negative-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
negative going edge of the clock pulse. The data on the J
and K inputs is allowed to change while the clock is HIGH
or LOW without affecting the outputs as long as setup and
hold times are not violated. A low logic level on the clear
input will reset the outputs regardless of the levels of the
Order Number Package Number
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
L X XX L
H ↓ HL H
H ↓ LH L
H ↓ HH
H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level
↓ = Negative going edge of pulse.
Q0 = The output logic level before the indicated input conditions were
Toggle = Each output changes to the complement of its previous level on
each falling edge of the clock pulse.
© 2000 Fairchild Semiconductor Corporation DS006372
Absolute Maximum Ratings(Note 1)
Operating Free Air Temperature Range
0°C to +70°C
Storage Temperature Range
−65°C to +150°C
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
VCC Supply Voltage
VIH HIGH Level Input Voltage
VIL LOW Level Input Voltage
IOH HIGH Level Output Current
IOL LOW Level Output Current
fCLK Clock Frequency (Note 2)
fCLK Clock Frequency (Note 3)
tSU Setup Time (Note 2)(Note 4)
tSU Setup Time (Note 3)(Note 4)
tH Hold Time (Note 2)(Note 4)
tH Hold Time (Note 3)(Note 4)
TA Free Air Operating Temperature
Note 2: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.
Note 3: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.
Note 4: The symbol (↓) indicates the falling edge of the clock pulse is used for reference.
|Features||DM74LS73A Dual Negative-Edge-Triggered M aster-Slave J-K Flip-Flops with Clear a nd Complementary Outputs August 1986 R evised March 2000 DM74LS73A Dual Negat ive-Edge-Triggered Master-Slave J-K Fli p-Flops with Clear and Complementary Ou tputs General Description This device c ontains two independent negative-edge-t riggered J-K flip-flops with complement ary outputs. The J and K data is proces sed by the flip-flops on the falling ed ge of the clock pulse. The clock trigge ring occurs at a voltage level and is n ot directly related to the transition t ime of the negative going edge of the c lock pulse. The data on the J and K inp uts is allowed to change while the cloc k is HIGH or LOW without affecting the outputs as long as setup and hold times are not violated. A low logic level on the clear input will reset the outputs regardless of the levels of the other inputs. Ordering Code: Order Number DM 74LS73AM DM74LS73AN Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circ.|
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