74LS74 SCHOTTKY Datasheet

74LS74 Datasheet, PDF, Equivalent


Part Number

74LS74

Description

LOW POWER SCHOTTKY

Manufacture

ON Semiconductor

Total Page 8 Pages
Datasheet
Download 74LS74 Datasheet


74LS74
SN74LS74A
Dual D-Type Positive
Edge-Triggered Flip-Flop
The SN74LS74A dual edge-triggered flip-flop utilizes Schottky
TTL circuitry to produce high speed D-type flip-flops. Each flip-flop
has individual clear and set inputs, and also complementary Q and Q
outputs.
Information at input D is transferred to the Q output on the
positive-going edge of the clock pulse. Clock triggering occurs at a
voltage level of the clock pulse and is not directly related to the
transition time of the positive-going pulse. When the clock input is at
either the HIGH or the LOW level, the D input signal has no effect.
MODE SELECT – TRUTH TABLE
OPERATING MODE
INPUTS
SD SD
D
OUTPUTS
QQ
Set
Reset (Clear)
*Undetermined
Load “1” (Set)
Load “0” (Reset)
LHXHL
HLXLH
L L XHH
HH h H L
HH l LH
* Both outputs will be HIGH while both SD and CD are LOW, but the output
states are unpredictable if SD and CD go HIGH simultaneously. If the levels
at the set and clear are near VIL maximum then we cannot guarantee to meet
the minimum level for VOH.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input
i, h (q) = (or output) one set-up time prior to the HIGH to LOW clock transition.
http://onsemi.com
LOW
POWER
SCHOTTKY
14
1
PLASTIC
N SUFFIX
CASE 646
14
1
SOIC
D SUFFIX
CASE 751A
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min Typ Max Unit
VCC Supply Voltage
TA Operating Ambient
Temperature Range
4.75 5.0 5.25
V
0 25 70 °C
IOH Output Current – High
IOL Output Current – Low
– 0.4
8.0
mA
mA
ORDERING INFORMATION
Device
Package
Shipping
SN74LS74AN 14 Pin DIP 2000 Units/Box
SN74LS74AD
14 Pin
2500/Tape & Reel
© Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1
Publication Order Number:
SN74LS74A/D

74LS74
SN74LS74A
LOGIC DIAGRAM (Each Flip-Flop)
SET (SD)4 (10)
CLEAR (CD)
1 (13)
CLOCK
3 (11)
D
2 (12)
Q
5 (9)
Q
6 (8)
LOGIC SYMBOL
4 10
2 D SD Q 5 12 D SD Q 9
3 CP
11 CP
CD Q 6
CD Q 8
1
VCC = PIN 14
GND = PIN 7
13
http://onsemi.com
2


Features SN74LS74A Dual D-Type Positive Edge-Trig gered Flip-Flop The SN74LS74A dual edge -triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-t ype flip-flops. Each flip-flop has indi vidual clear and set inputs, and also c omplementary Q and Q outputs. Informati on at input D is transferred to the Q o utput on the positive-going edge of the clock pulse. Clock triggering occurs a t a voltage level of the clock pulse an d is not directly related to the transi tion time of the positive-going pulse. When the clock input is at either the H IGH or the LOW level, the D input signa l has no effect. http://onsemi.com LOW POWER SCHOTTKY MODE SELECT – TRUTH TABLE INPUTS OPERATING MODE SD Set Rese t (Clear) *Undetermined Load “1” (S et) Load “0” (Reset) * L H L H H SD H L L H H D X X X h l Q H L H H L Q L H H L H 14 1 OUTPUTS PLASTIC N SUFFIX CASE 646 Both outputs will be HIGH wh ile both SD and CD are LOW, but the out put states are unpredictable if SD and CD go HIGH simultaneously. If the .
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