74LS74 Flip-Flops Datasheet

74LS74 Datasheet, PDF, Equivalent


Part Number

74LS74

Description

Dual Positive-Edge-Triggered D Flip-Flops

Manufacture

Fairchild Semiconductor

Total Page 6 Pages
Datasheet
Download 74LS74 Datasheet


74LS74
August 1986
Revised March 2000
DM74LS74A
Dual Positive-Edge-Triggered D Flip-Flops with
Preset, Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered D flip-flops with complementary outputs. The infor-
mation on the D input is accepted by the flip-flops on the
positive going edge of the clock pulse. The triggering
occurs at a voltage level and is not directly related to the
transition time of the rising edge of the clock. The data on
the D input may be changed while the clock is LOW or
HIGH without affecting the outputs as long as the data
setup and hold times are not violated. A low logic level on
the preset or clear inputs will set or reset the outputs
regardless of the logic levels of the other inputs.
Ordering Code:
Order Number Package Number
Package Description
DM74LS74AM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS85ASJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS74AN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Outputs
PR CLR CLK D
Q
Q
LHXX
H
L
HLXX
L
H
L L X X H (Note 1) H (Note 1)
HHH
H
L
HHL
L
H
HH L X
Q0
Q0
H = HIGH Logic Level
X = Either LOW or HIGH Logic Level
L = LOW Logic Level
↑ = Positive-going Transition
Q0 = The output logic level of Q before the indicated input conditions were
established.
Note 1: This configuration is nonstable; that is, it will not persist when either
the preset and/or clear inputs return to their inactive (HIGH) level.
© 2000 Fairchild Semiconductor Corporation DS006373
www.fairchildsemi.com

74LS74
Absolute Maximum Ratings(Note 2)
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range
65°C to +150°C
Note 2: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
Parameter
Min
VCC Supply Voltage
4.75
VIH HIGH Level Input Voltage
2
VIL LOW Level Input Voltage
IOH HIGH Level Output Current
IOL LOW Level Output Current
fCLK Clock Frequency (Note 3)
0
fCLK Clock Frequency (Note 4)
0
tW Pulse Width
Clock HIGH
18
(Note 3)
Preset LOW
15
Clear LOW
15
tW Pulse Width
(Note 4)
Clock HIGH
Preset LOW
25
20
Clear LOW
20
tSU Setup Time (Note 3)(Note 5)
20
tSU Setup Time (Note 4)(Note 5)
25
tH Hold Time (Note 5)(Note 6)
0
TA Free Air Operating Temperature
0
Note 3: CL = 15 pF, RL = 2 k, TA = 25°C, and VCC = 5V.
Note 4: CL = 50 pF, RL = 2 k, TA = 25°C, and VCC = 5V.
Note 5: The symbol () indicates the rising edge of the clock pulse is used for reference.
Note 6: TA = 25°C and VCC = 5V.
Nom
5
Max
5.25
0.8
0.4
8
25
20
70
Units
V
V
V
mA
mA
MHz
MHz
ns
ns
ns
ns
ns
°C
www.fairchildsemi.com
2


Features DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Comp lementary Outputs August 1986 Revised March 2000 DM74LS74A Dual Positive-Edg e-Triggered D Flip-Flops with Preset, C lear and Complementary Outputs General Description This device contains two in dependent positive-edge-triggered D fli p-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive goin g edge of the clock pulse. The triggeri ng occurs at a voltage level and is not directly related to the transition tim e of the rising edge of the clock. The data on the D input may be changed whil e the clock is LOW or HIGH without affe cting the outputs as long as the data s etup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs r egardless of the logic levels of the ot her inputs. Ordering Code: Order Numbe r DM74LS74AM DM74LS85ASJ DM74LS74AN Pac kage Number M14A M14D N14A Package Description 14-Lead Small Ou.
Keywords 74LS74, datasheet, pdf, Fairchild Semiconductor, Dual, Positive-Edge-Triggered, D, Flip-Flops, 4LS74, LS74, S74, 74LS7, 74LS, 74L, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)