74LS74

SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs. Information at input D is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or the LOW level, the D input signal has no effect. DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY LOGIC DIAGRAM (Each Flip-Flop) 14 1 J SUFFIX CERAMIC CASE 632-08 SET (SD) 4 (10) Q 5 (9) CLEAR (CD) 1 (13) CLOCK 3 (11) D 2 (12) 14 N SUFFIX PLASTIC CASE 646-06 1 Q 6 (8) 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MODE SELECT — TRUTH TABLE INPUTS OPERATING MODE SD Set Reset (Clear) *Undetermined Load “1” (Set) Load “0” (Reset) L H L H H SD H L L H H D X X X h l Q H L H H L Q L H H L H OUTPUTS SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC LOGIC SYMBOL 4 2 3 D SD Q CP CD Q 1 VCC = PIN 14 GND = PIN 7 6 5 12 11 10 D SD Q CP CD Q 13 8 9 * Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously. If the levels at the set and clear are near VIL maximum then we cannot guarantee to meet the minimum level for VOH. H, h = HI...