74LS75 LATCH Datasheet

74LS75 Datasheet, PDF, Equivalent


Part Number

74LS75

Description

4-BIT D LATCH

Manufacture

Motorola

Total Page 4 Pages
Datasheet
Download 74LS75 Datasheet


74LS75
4-BIT D LATCH
The TTL/MSI SN54/ 74LS75 and SN54/ 74LS77 are latches used as tem-
porary storage for binary information between processing units and input /out-
put or indicator units. Information present at a data (D) input is transferred to
the Q output when the Enable is HIGH and the Q output will follow the data
input as long as the Enable remains HIGH. When the Enable goes LOW, the
information (that was present at the data input at the time the transition oc-
curred) is retained at the Q output until the Enable is permitted to go HIGH.
The SN54 / 74LS75 features complementary Q and Q output from a 4-bit
latch and is available in the 16-pin packages. For higher component density
applications the SN54/ 74LS77 4-bit latch is available in the 14-pin package
with Q outputs omitted.
CONNECTION DIAGRAMS DIP (TOP VIEW)
Q0 Q1 Q1 E0–1 GND Q2 Q2 Q3
16 15 14 13 12 11 10 9
SN54 / 74LS75
1 2 3 4 56 78
Q0 D0 D1 E2–3 VCC D2 D3 Q3
Q0 Q1 E0–1 GND NC Q2 Q3
14 13 12 11 10 9 8
SN54 / 74LS77
1234567
D0 D1 E2–3 VCC D2 D3 NC
PIN NAMES
LOADING (Note a)
HIGH
LOW
D1–D4
E0–1
E2–3
Q1–Q4
Q1–Q4
Data Inputs
Enable Input Latches 0, 1
Enable Input Latches 2, 3
Latch Outputs (Note b)
Complimentary Latch Outputs (Note b)
0.5 U.L.
2.0 U.L.
2.0 U.L.
10 U.L.
10 U.L.
0.25 U.L.
1.0 U.L.
1.0 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a) 1 Unit Load (U.L.) = 40 µA HIGH.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
TRUTH TABLE
(Each latch)
tn tn + 1
DQ
HH
LL
NOTES:
tn = bit time before enable
negative-going transition
tn+1 = bit time after enable
negative-going transition
SN54/74LS75
SN54/74LS77
4-BIT D LATCH
LOW POWER SCHOTTKY
16
1
16
1
16
1
14
1
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
D SUFFIX
SOIC
CASE 751B-03
J SUFFIX
CERAMIC
CASE 632-08
14
1
14
1
N SUFFIX
PLASTIC
CASE 646-06
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
FAST AND LS TTL DATA
5-75

74LS75
SN54 / 74LS75
LOGIC SYMBOLS
SN54/74LS75
2367
D0 D1 D2 D3
13 E0–1
4 E2–3
VCC = PIN 5
GND = PIN 12
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
16 1 15 14 10 11 9 8
SN54/74LS77
1 25 6
D0 D1 D2 D3
12 E0–1
VCC = PIN 4
3 E2–3
GND = PIN 11
NC = PIN 7, 10
Q0 Q1 Q2 Q3
14 13 9 8
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage
54
74
0.7 Guaranteed Input LOW Voltage for
0.8 V All Inputs
VIK
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
54
74
– 0.65
– 1.5
2.5 3.5
2.7 3.5
V VCC = MIN, IIN = – 18 mA
V VCC = MIN, IOH = MAX, VIN = VIH
V or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
74
0.25 0.4
0.35 0.5
V IOL = 4.0 mA VCC = VCC MIN,
VIN = VIL or VIH
V IOL = 8.0 mA per Truth Table
IIH Input HIGH Current
D Input
E Input
D Input
E Input
20 µA VCC = MAX, VIN = 2.7 V
80
0.1 mA VCC = MAX, VIN = 7.0 V
0.4
IIL Input LOW Current
D Input
E Input
– 0.4
–1.6
mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1)
– 20
ICC Power Supply Current
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
–100
12
mA VCC = MAX
mA VCC = MAX
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Symbol
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Parameter
Propagation Delay, Data to Q
Propagation Delay, Data to Q
Propagation Delay, Enable to Q
Propagation Delay, Enable to Q
Min
Limits
Typ
15
9.0
12
7.0
15
14
16
7.0
Max
27
17
20
15
27
25
30
15
Unit
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
FAST AND LS TTL DATA
5-76


Features 4-BIT D LATCH The TTL/MSI SN54/ 74LS75 a nd SN54/ 74LS77 are latches used as tem porary storage for binary information b etween processing units and input /outp ut or indicator units. Information pres ent at a data (D) input is transferred to the Q output when the Enable is HIGH and the Q output will follow the data input as long as the Enable remains HIG H. When the Enable goes LOW, the inform ation (that was present at the data inp ut at the time the transition occurred) is retained at the Q output until the Enable is permitted to go HIGH. The SN5 4 / 74LS75 features complementary Q and Q output from a 4-bit latch and is ava ilable in the 16-pin packages. For high er component density applications the S N54/ 74LS77 4-bit latch is available in the 14-pin package with Q outputs omit ted. CONNECTION DIAGRAMS DIP (TOP VIEW) Q0 16 Q1 15 Q1 14 E0–1 GND 13 12 Q2 11 Q2 10 Q3 9 16 SN54/74LS75 SN54/74LS 77 4-BIT D LATCH LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 1 SN54 / 74LS75 N SUFFIX PLASTIC CAS.
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