74LV125

INTEGRATED CIRCUITS 74LV125 Quad buffer/line driver (3-State) Product specification Supersedes data of 1997 Feb 03 IC24 Data Handbook 1998 Apr 28 Philips Semiconductors Philips Semiconductors Product specification Quad buffer/line driver (3-State) 74LV125 FEATURES Wide operating voltage: 1.0 to 5.5 V Optimized for Low Voltage applications: 1.0 to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Output capability: bus driver ICC category: MSI QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL tPHL/tPLH CI CPD PARAMETER Propagation delay nA to nY Input capacitance Power dissipation capacitance per buffer Tamb = 25°C. Tamb = 25°C. DESCRIPTION The 74LV125 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT125. The 74LV125 consists of four non-inverting buffers/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high impedance OFF-state. CONDITIONS CL = 15 pF; VCC = 3.3 V VCC = 3.3 V; VI = GND to VCC1 TYPICAL 9 3.5 22 UNIT ns pF pF NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi )ȍ (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in...