74LVC109

INTEGRATED CIRCUITS 74LVC109 Dual JK flip-flop with set and reset; positive-edge trigger Product specification Supersedes data of 1997 Mar 18 IC24 Data Handbook 1998 Apr 28 Philips Semiconductors Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74LVC109 FEATURES Wide supply voltage range of 1.2 to 3.6 V In accordance with JEDEC standard no. 8-1A. Inputs accept voltages up to 5.5 V CMOS low power consumption Direct interface with TTL levels Output capability: standard ICC category: flip-flops DESCRIPTION The 74LVC109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. The 74LVC109 is a dual positive-edge triggered JK-type flip-flop featuring individual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by tying the J and K inputs together. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL tPHL/tPLH fmax CI C...