Document
TC74VHC299F/FT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHC299F, TC74VHC299FT
8-Bit PIPO Shift Register with Asynchronous Clear
The TC74VHC299 is an advanced high speed CMOS 8-BIT PIPO SHIFT REGISTER fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.
It has a four modes (HOLD, SHIFT LEFT, SHIFT RIGHT and LOAD DATA) controlled by the two selection inputs (S0, S1).
When one or both enable ( G1 , G2 ) are high, the eight I/O are forced to the high-impedance state; however, sequential operation or clearing of the register is not affected.
All inputs are equipped with protection circuits against static discharge.
Features (Note 1) (Note 2) (Note 3)
• High speed: fmax = 160 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Balanced propagation delays: tpLH ∼− tpHL • Wide operating voltage range: VCC (opr) = 2 to 5.5 V • Low noise: VOLP = 1.2 V (max) • Pin and function compatible with 74ALS299
TC74VHC299F
TC74VHC299FT
Weight SOP20-P-300-1.27A TSSOP20-P-0044-0.65A
: 0.22 g (typ.) : 0.08 g (typ.)
Note 1: Do not apply a signal to A/QA to H/QH bus terminal when it is in the output mode. Damage may result.
Note 2: All floating (high impedance) A/QA to H/QH bus terminals must have their input levels fixed by means of pull up or pull down resistors.
Note 3: A parasitic diode is formed between A/QA to H/QH bus and VCC terminals. Therefore bus terminal can not be used to interface 5 V to 3 V systems directly.
Start of commercial production
1992-10
1
2014-03-01
Pin Assignment
TC74VHC299F/FT
IEC Logic Symbol
S0 1 G1 2 G2 3 G/QG 4 E/QE 5 C/QC 6 A/QA 7 QA’ 8 CLR 9 GND 10
(top view)
20 VCC 19 S1 18 SL 17 QH’ 16 H/QH 15 F/QF 14 D/QD 13 B/QB 12 CK 11 SR
CLR (9) G1 (2) G2 (3) (1) S0 (19) S1 (12) CK (11) SR (7)
A/QA
(13) B/QB
(6) C/QC
(14) D/QD
(5) E/QE
(15) F/QF
(4) G/QG
(16) H/QH
(18) SL
R SRG 8 & 3 EN 13
0 M0 13
C4/1→/2←
1, 4D
3, 4D
5, 13
Z5
3, 4D Z6
6, 13
3, 4D
12, 13
Z12
2, 4D
(8) QA’
(17) QH’
Truth Table
Mode
CLR
Z
L
L Clear
L
Hold
H
H Shift Right
H
H Shift Left
H
Load
H
Function Select
S1 S0
H
H
L
X
X
L
L
L
L
H
L
H
H
L
H
L
H
H
Inputs
Output Control
G1
G2
CK
(Note)
(Note)
X
X
X
L
L
X
L
L
X
L
L
X
L
L
L
L
L
L
L
L
X
X
Serial SL SR
Inputs /Outputs
A/QA H/QH
Outputs QA’ QH’
X
X
Z
Z
L
L
X
X
L
L
L
L
X
X
L
L
L
L
X
X QA0 QH0 QA0 QH0
X
H
H QGn H QGn
X
L
L QGn L QGn
H
X QBn H QBn H
L
X QBn L QBn L
X
X
a
h
a
h
Note:
When one or both output controls are high, the eight input/output terminals are in the high-impedance state; however sequential or clearing of the register is not affected.
Z: High impedance Qn0: The level of Qn before the indicated steady-state input conditions were established. Qnn: The level of Qn before the most recent active transition indicated by ↓ or ↑. a, h: The level of the steady-state inputs A, H, respectively. X: Don’t care.
2
2014-03-01
Timing Chart
CK
Mode Control S0 Inputs S1
Serial Data Inputs
CLR SR SL
Outputs QA’
A/QA
B/QB
C/QC
Inputs/ Outputs
D/QD E/QE
F/QF
G/QG
H/QH
Outputs QH’
CLEAR LOAD
SHIFT RIGHT
TC74VHC299F/FT
SHIFT LEFT
HOLD CLEAR
3
2014-03-01
System Diagram
1 S0
19 S1
TC74VHC299F/FT
SL 18
QH’17 CK DQ
R
16 H/QH
CK DQ
R
4 G/QG
CK DQ
R
15 F/QF
CK DQ
R
5 E/QE
CK DQ
R
14 D/QD
CK DQ
R
6 C/QC
CK DQ
R
13 B/QB
CK DQ
R
7 A/QA
11 SR
12 CK
8 92 3 QA’ CLR G1 G2
4
2014-03-01
Absolute Maximum Ratings (Note)
TC74VHC299F/FT
Characteristics
Symbol
Rating
Unit
Supply voltage range DC input voltage DC bus I/O voltage (A/QA to H/QH’) DC output voltage (QA’ to QH’) Input diode current Output diode current DC output current DC VCC/ground current Power dissipation Storage temperature
VCC
−0.5 to 7.0
V
VIN
−0.5 to 7.0
V
VIN/OUT
−0.5 to VCC + 0.5
V
VOUT
IIK IOK IOUT ICC PD Tstg
−0.5 to VCC + 0.5
V
−20
mA
±20
mA
±25
mA
±80
mA
180
mW
−65 to 150
°C
Note:
Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc).
Operating Ranges (Note)
Characteristi.