2-INPUT NAND GATE
CMOS Digital Integrated Circuits Silicon Monolithic
TC7SET00FU
TC7SET00FU
1. Functional Description
• 2-Input NAND Gat...
Description
CMOS Digital Integrated Circuits Silicon Monolithic
TC7SET00FU
TC7SET00FU
1. Functional Description
2-Input NAND Gate
2. Features
(1) AEC-Q100 (Rev. H) (Note 1) (2) Wide operating temperature range: Topr = -40 to 125 (Note 2) (3) High speed operation: tpd = 4.2 ns (typ.) (VCC = 5.0 V, CL = 15 pF) (4) Low power dissipation: ICC = 2.0 µA (max) (Ta = 25 ) (5) Compatible with TTL outputs: VIL = 0.8 V (max)
VIH = 2.0 V (min) (6) 5.5 V tolerant inputs (7) Balanced Propagation Delay: tPLH ≈ tPHL
Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales representative.
Note 2: For devices with the ordering part number ending in J(CT. Topr = -40 to 85 for the other devices.
3. Packaging
USV
©2016 Toshiba Corporation
1
Start of commercial production
1996-09
2017-05-16 Rev.3.0
4. Marking and Pin Assignment
TC7SET00FU
Marking
5. IEC Logic Symbol
Pin Assignment (Top view)
6. Truth Table
ABY
L LH L HH HLH HH...
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