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TD62C805F Dataheets PDF



Part Number TD62C805F
Manufacturers Toshiba
Logo Toshiba
Description 48BIT THERMAL HEAD DRIVER
Datasheet TD62C805F DatasheetTD62C805F Datasheet (PDF)

TD62C805F TOSHIBA Bi−CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC TD62C805F 48BIT THERMAL HEAD DRIVER The TD62805F is a general purpose 48bit driver IC consisting of 8 block 8bit shift register and 48bit drivers (Open Drain). This device is best suited as a 48 dot thermal printer head drivers. FEATURES l 8bit parallel input and 6 block 8bit shift register l CMOS compatible input. l High driverability ·········· 30 V / 100 mA / ch l Built in monostable multivibrator for head protection l 16 steps .

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TD62C805F TOSHIBA Bi−CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC TD62C805F 48BIT THERMAL HEAD DRIVER The TD62805F is a general purpose 48bit driver IC consisting of 8 block 8bit shift register and 48bit drivers (Open Drain). This device is best suited as a 48 dot thermal printer head drivers. FEATURES l 8bit parallel input and 6 block 8bit shift register l CMOS compatible input. l High driverability ·········· 30 V / 100 mA / ch l Built in monostable multivibrator for head protection l 16 steps gray scale operating with 4bit data l 48bit open drain outputs l Package ·························· µPFP−80 pin Weight: 1.53 g (Typ.) 1 2001-07-05 PIN CONNECTION (TOP VIEW) TD62C805F 2 2001-07-05 BLOCK DIAGRAM TD62C805F 3 2001-07-05 PIN FUNCTION TD62C805F PIN No. 24 25 37 28~36 26 38 39 40 42 41 43 22 23, 44 ― 27, 32 PIN NAME CLK WRITE·CLK RESET DATA1~8 OUT / PWM PWM COUNTER·CLOCK OUT· E E ·CLK WRITE· E MMV / E MO VDD VSS (O) VSS (L) FUNCTION “ ” : Data shift “H” : enable clock signal, “L” : disable clock signal pull−up input terminal “L” : all outputs “OFF”, reset PWM counter reset PWM counter and MMV circuit Pull−up input terminal Input terminals for output data “H” : output “ON”, “L” : output “OFF” And input terminals for PWM data “H” : enable output data for shift register “L” : enable PWM data for counter “L” : output enable (PWM operating) Input terminal for clock of PWM counter and for trigger of MMV “L” : all outputs “ON” “ ” : outputs “OFF” when OUT·E is “High”. Outputs “ON” when OUT·E is “Low”. Pull−up input terminal “H” : enable E−CLK signal pull−up input terminal CR connection terminal for MMV ON / OFF monitor terminal of output OF8 Supply voltage terminal for control logic GND terminals for driver PIN No. : 2, 3, 12, 21, 45, 54, 63, 64, 73 GND terminals for control logic 4 2001-07-05 TD62C805F (1) Data Input D1~D6 of Input Dates are entered to shift Register by the clock signal with the timing of rise. Outputs are latched by holding the WRITE·CLK “Low” or to stop the clock signal. PWM Data (DATA1~4) are latched by OUT / PWM signal “Low”. (2) Output Enable Outputs become “OFF” at the first rising edge of E·CLK after the OUT·E to “High”, and become “ON” at the first rising edge of E·CLK after the OUT·E to “Low”. Output ON / OFF duty is controlled by controlling OUT·E signal directly or to change the timing of WRITE·E and E·CLK. 5 2001-07-05 TD62C805F (3) PWM Control Outputs ON / OFF duty are controlled by OUT· E and PWM DATA of D1~D4 PWM control is performed by comparing the internal 4bit PWM Counter out and PWM DATA of D1~D4. For example, when PWM DATA is 7, 50% Output Duty is obtained. (Refer to tables below.) PWM DATA Duty (%) 0 0 123456789 6.25 12.50 18.75 25.00 31.25 37.50 43.75 50.00 56.25 PWM DATA Duty (%) A 62.50 B 68.75 C 75.00 D 81.25 E 87.50 F 100.00 6 2001-07-05 TD62C805F MMV OPERATION MMV output of Q becomes “L” when the MMV / E voltage becomes less than Vref (L) after the first rising edge of INTERNAL CLOCK. And becomes “H” when the MMV / E voltage above Vref (H) after re−charging of external capacitance connect to MMV / E. The external capacitance and Resistor connect to MMV / E control MMV Output “ON” period. So Output Load is protected from burn−out. It’s required enough discharging time of external capacitance. (Refer to figure below) ● Pulse width of MMV 7 2001-07-05 INPUT CIRCUIT 1. DATA1~8, CLK, COUNTER·CLK, OUT /PWM , OUT· E TD62C805F 2. E ·CLK, RESET , WRITE· E , WRITE·CLK 3. PWM OUTPUT CIRCUIT 1. OA1~ 8 ~ OF1~ 8 8 2001-07-05 MAXIMUM RATINGS (Ta = 25°C) CHARACTERISTIC SYMBOL RATING Supply Voltage Output Voltage Output Current Input Current Input Voltage Power Dissipation Free Air On PCB (Note) Operating Temperature Storage Temperature VDD VDS IDS IIN VIN PD Topr Tstg 7 30 100 ±5 −0.4~VDD±0.4 1.0 1.3 −40~85 −55~150 Note: On Glass Epoxy PCB (100 × 100 × 1.6 mm, Cu 40%) UNIT V V mA / ch mA V W °C °C RECOMMENDED OPERATING CONDITIONS (Ta = −40~85°C) CHARACTERISTIC Output Voltage Supply Voltage Output Current Input Voltage Operating Clock Frequency Clock Pulse Width Data Set−Up Time Data Hold Time SYMBOL TEST CONDITION VDS VDD IDS VIN fCLK tw tsetup thold ― ― Duty 50% Duty 80% Duty 100% ― Duty 50% COUNTER·CLK CLK ― TD62C805F MIN TYP. MAX UNIT ― ― 26 V 4.5 ― 5.5 V ― ― 33.3 ― ― 26.4 mA /ch ― ― 23.6 GND ― VDD V ―― 5 MHz 50 ― ― ns 20 ― ― ns 9 2001-07-05 TD62C805F ELECTRICAL CHARACTERISTICS (Ta = 25°C, VDD = 5.5 V) CHARACTERISTIC Input Voltage Input Current “H” Level “L” Level WRITE·CLK E ·CLK, RESET WRITE· E SYMBOL VIH VIL TEST CIR− CUIT ― ― TEST CONDITION ― ― IINH ― VIN = 0 V, VDD = 5 V MIN TYP. MAX UNIT 3.5 ― VDD + 0.4 V −0.4 ― 1.5 −34 −70 −145 µA PWM Output Voltage Output On Resistor Output Leak Current Quiescent Current Operating Supply Current IINL VDS RON IOZ IDD IDDopr ― VIN = 5 V, VDD = 5 V ― OA1~OF8 IDS = 80 mA IDS = 50 mA ― IDS = 50 mA ― VDS = 30 V ―― ― VDD = 5 V, fCLK = 5MHz O.


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