HYB511000BJL-70

1 M × 1-Bit Dynamic RAM Low Power 1 M × 1-Bit Dynamic RAM HYB 511000BJ-50/-60/-70 HYB 511000BJL-50/-60/-70 Advanced Information 1 048 576 words by 1-bit organization Fast access and cycle time 50 ns access time 95 ns cycle time (-50 version) 60 ns access time 130 ns cycle time (-60 version) 70 ns access time 130 ns cycle time (-70 version) Fast page mode cycle time 35 ns (-50 version) 40 ns (-60 version) 45 ns (-70 version) Low power dissipation max. 495 mW active (-50 version) max. 440 mW active (-60 version) max. 385 mW active (-70 version) max. 5.5 mW standby max. 1.1 mW standby for L-version Single + 5 V (± 10 %) supply with a built-in VBB generator Output unlatched at cycle end allows twodimensional chip selection Common I/O capability using “early write” operation Read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden-refresh, fast page mode capability and test mode capability All inputs, outputs and clocks TTL-compatible 512 refresh cycles/8 ms 512 refresh cycles/64 ms for L-version only Plastic Packages: P-SOJ-26/20-1 Ordering Information Type HYB 511000BJ-50 HYB 511000BJ-60 HYB 511000BJ-70 HYB 511000BJL-50 HYB 511000BJL-60 HYB 511000BJL-70 Ordering Code Q67100-Q1056 Q67100-Q518 Q67100-Q519 on request Q67100-Q526 Q67100-Q527 Package P-SOJ-26/20-1 P-SOJ-26/20-1 P-SOJ-26/20-1 P-SOJ-26/20-1 P-SOJ-26/20-1 P-SOJ-26/20-1 Description DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DR...