HYB5116405BT-60

4M x 4-Bit Dynamic RAM 2k & 4k Refresh (Hyper Page Mode- EDO) Advanced Information 4 194 304 words by 4-bit organization 0 to 70 °C operating temperature Performance: -50 tRAC tCAC tAA tRC tHPC RAS access time CAS access time Access time from address Read/Write cycle time Hyper page mode (EDO) cycle time 50 13 25 84 20 HYB5116405BJ/BT -50/-60/-70 HYB5117405BJ/BT -50/-60/-70 -60 60 15 30 104 25 -70 70 20 35 124 30 ns ns ns ns ns Single + 5 V (± 10 %) supply Low power dissipation max. 550 mW active (HYB5116405BJ/BT-50) max. 495 mW active (HYB5116405BJ/BT-60) max. 440 mW active (HYB5116405BJ/BT-70) max. 660 mW active (HYB5117405BJ/BT-50) max. 605 mW active (HYB5117405BJ/BT-60) max. 550 mW active (HYB5117405BJ/BT-70) 11 mW standby (TTL) 5.5. mW standby (MOS) Output unlatched at cycle end allows two-dimensional chip selection Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh, self refresh and test mode Hyper page mode (EDO) capability All inputs, outputs and clocks fully TTL-compatible 4096 refresh cycles / 64 ms for HYB5116405BJ/BT (4k-Refresh) 2048 refresh cycles / 32 ms for HYB5117405BJ/BT (2k-Refresh) Plastic Package: P-SOJ-26/24 300 mil P TSOPII-26/24 300 mil Semiconductor Group 1 1.96 HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM The HYB 5116(7)405BJ/BT is a 16MBit dynamic RAM organized as 4194304 words by 4-bits. The HYB 5116(7)405BJ/BT utilizes a submicron CMOS silicon gate process technology, as we...