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HYB5117405BT-60 Dataheets PDF



Part Number HYB5117405BT-60
Manufacturers Siemens
Logo Siemens
Description 4M x 4-Bit Dynamic RAM 2k & 4k Refresh
Datasheet HYB5117405BT-60 DatasheetHYB5117405BT-60 Datasheet (PDF)

4M x 4-Bit Dynamic RAM 2k & 4k Refresh (Hyper Page Mode- EDO) Advanced Information 4 194 304 words by 4-bit organization 0 to 70 °C operating temperature Performance: -50 tRAC tCAC tAA tRC tHPC RAS access time CAS access time Access time from address Read/Write cycle time Hyper page mode (EDO) cycle time 50 13 25 84 20 HYB5116405BJ/BT -50/-60/-70 HYB5117405BJ/BT -50/-60/-70 • • • -60 60 15 30 104 25 -70 70 20 35 124 30 ns ns ns ns ns • • • • • • • • • Single + 5 V (± 10 %) supply Low powe.

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4M x 4-Bit Dynamic RAM 2k & 4k Refresh (Hyper Page Mode- EDO) Advanced Information 4 194 304 words by 4-bit organization 0 to 70 °C operating temperature Performance: -50 tRAC tCAC tAA tRC tHPC RAS access time CAS access time Access time from address Read/Write cycle time Hyper page mode (EDO) cycle time 50 13 25 84 20 HYB5116405BJ/BT -50/-60/-70 HYB5117405BJ/BT -50/-60/-70 • • • -60 60 15 30 104 25 -70 70 20 35 124 30 ns ns ns ns ns • • • • • • • • • Single + 5 V (± 10 %) supply Low power dissipation max. 550 mW active (HYB5116405BJ/BT-50) max. 495 mW active (HYB5116405BJ/BT-60) max. 440 mW active (HYB5116405BJ/BT-70) max. 660 mW active (HYB5117405BJ/BT-50) max. 605 mW active (HYB5117405BJ/BT-60) max. 550 mW active (HYB5117405BJ/BT-70) 11 mW standby (TTL) 5.5. mW standby (MOS) Output unlatched at cycle end allows two-dimensional chip selection Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh, self refresh and test mode Hyper page mode (EDO) capability All inputs, outputs and clocks fully TTL-compatible 4096 refresh cycles / 64 ms for HYB5116405BJ/BT (4k-Refresh) 2048 refresh cycles / 32 ms for HYB5117405BJ/BT (2k-Refresh) Plastic Package: P-SOJ-26/24 300 mil P TSOPII-26/24 300 mil Semiconductor Group 1 1.96 HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM The HYB 5116(7)405BJ/BT is a 16MBit dynamic RAM organized as 4194304 words by 4-bits. The HYB 5116(7)405BJ/BT utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 5116(7)405BJ/BT to be packaged in a standard SOJ 26/24 or TSOPII-26/24 plastic package, both with 300 mil width. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. System-oriented features include single + 5 V (± 10 %) power supply, direct interfacing with high-performance logic device families such as Schottky TTL. Ordering Information Type HYB 5116405BJ-50 HYB 5116405BJ-60 HYB 5116405BJ-70 HYB 5116405BT-50 HYB 5116405BT-60 HYB 5116405BT-70 HYB 5117405BJ-50 HYB 5117405BJ-60 HYB 5117405BJ-70 HYB 5117405BT-50 HYB 5117405BT-60 HYB 5117405BT-70 Pin Names A0-A11 A0-A9 A0-A10 RAS OE I/O1-I/O4 CAS WE Row Address Inputs for HYB5116405 Column Address Inputs for HYB5116405 Row and Column Address Inputs for HYB5117405 Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply (+ 5 V) Ground (0 V) not connected Ordering Code Q67100-Q1098 Q67100-Q1099 Q67100-Q1100 on request on request on request Q67100-Q1101 Q67100-Q1102 Q67100-Q1103 on request on request on request Package P-SOJ-26/24 300 mil P-SOJ-26/24 300 mil P-SOJ-26/24 300 mil P-TSOPII-26/24 300mil P-TSOPII-26/24 300mil P-TSOPII-26/24 300mil P-SOJ-26/24 300 mil P-SOJ-26/24 300 mil P-SOJ-26/24 300 mil P-TSOPII-26/24 300mil P-TSOPII-26/24 300mil P-TSOPII-26/24 300mil Descriptions DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) VCC VSS N.C. Semiconductor Group 2 HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM P-SOJ-26/24 300 mil P-TSOPII-26/24 300 mil Vcc I/O1 I/O2 WE RAS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 Vss I/O4 I/O3 CAS OE A9 A8 A7 A6 A5 A4 Vss Vcc I/O1 I/O2 WE RAS NC A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 Vss I/O4 I/O3 CAS OE A9 A8 A7 A6 A5 A4 Vss HYB 5116405 BJ/BT HYB 5117405 BJ/BT Pin Configuration Semiconductor Group 3 HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM I/O1 I/O2 I/O3 I/O4 WE CAS . & Data in Buffer No. 2 Clock Generator Data out Buffer 4 OE 4 10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 12 Column Address Buffer(10) 10 Column Decoder Refresh Controller Sense Amplifier I/O Gating 4 Refresh Counter (12) 12 Row 1024 x4 Address Buffers(12) 12 Decoder 4096 Row Memory Array 4096x1024x4 RAS No. 1 Clock Generator Voltage Down Generator VCC VCC (internal) Block Diagram for HYB 5116405 Semiconductor Group 4 HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM I/O1 I/O2 I/O3 I/O4 WE CAS . & Data in Buffer No. 2 Clock Generator Data out Buffer 4 OE 4 11 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 11 Column Address Buffer(11) 11 Column Decoder Refresh Controller Sense Amplifier I/O Gating 4 Refresh Counter (11) 11 Row 2048 x4 Address Buffers(11) 11 Decoder 2048 Row Memory Array 2048x2048x4 RAS No. 1 Clock Generator Voltage Down Generator VCC VCC (internal) Block Diagram for HYB 5117405 Semiconductor Group 5 HYB5116(7)405BJ/BT-50/-60/-70 4M x 4-EDO DRAM Absolute Maximum Ratings Operating temperature range ...............


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