HYB514405BJL-70

1M x 4-Bit Dynamic RAM (Hyper Page Mode (EDO) version) HYB 514405BJ/BJL-50/-60/-70 Preliminary Information 1 048 576 words by 4-bit organization 0 to 70 ˚C operating temperature Hyper Page Mode - EDO Performance: -50 -60 60 15 30 104 25 -70 70 20 35 124 30 ns ns ns ns ns tRAC tCAC tAA tRC tHPC RAS access time CAS access time Access time from address Read/Write cycle time Hyper page mode (EDO) cycle time 50 13 25 89 20 Single + 5 V (± 10 %) supply Low power dissipation max. 660 mW active (-50 version) max. 605 mW active (-60 version) max. 550 mW active (-70 version) Standby power dissipation: 11 mW max.standby (TTL) 5.5 mW max.standby (CMOS) 1.1 mW max.standby (CMOS) for Low Power Version Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh and test mode capability All inputs and outputs TTL-compatible 1024 refresh cycles / 16 ms 1024 refresh cycles / 128 ms for Low Power Version Plastic Packages: P-SOJ-26/20-5 with 300 mil width Semiconductor Group 1 5.96 HYB 514405BJ/BLJ-50/-60/-70 1M x 4 EDO - DRAM The HYB 514405BJ is the new generation dynamic RAM organized as 1 048 576 words by 4-bit. The HYB 514405BJ utilizes CMOS silicon gate process as well as advances circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 514405BJ to be packed in a standard plastic P-SOJ-26/20 package. This package size provides high system bit d...