Document
1M x 32-Bit Dynamic RAM Module (2M x 16-Bit Dynamic RAM Module)
HYM 321160S/GS-60/-70
Advanced Information
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1 048 576 words by 32-bit organization (alternative 2 097 152 words by 16-bit) Fast access and cycle time 60 ns access time 110 ns cycle time (-60 version) 70 ns access time 130 ns cycle time (-70 version) Fast page mode capability with 40 ns cycle time (-60 version) 45 ns cycle time (-70 version) Single + 5 V (± 10 %) supply Low power dissipation max. 4840 mW active (-60 version) max. 4400 mW active (-70 version) CMOS – 44 mW standby TTL – 88 mW standby
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CAS-before-RAS refresh, RAS-only-refresh, Hidden refresh 8 decoupling substrate capacitors mounted on
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All inputs, outputs and clock fully TTL compatible 72 pin Single in-Line Memory Module Utilizes eight 1M × 4-DRAMs in 300 mil SOJ packages 1024 refresh cycles /16 ms Tin-Lead contact pads (S - version) Gold contact pads (GS - version) single sided module with 25.4 mm (1000 mil) height
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Ordering Information Type HYM 321160S-60 HYM 321160S-70 HYM 321160GS-60 HYM 321160GS-70 Ordering Code Q67100-Q2010 on request Q67100-Q2009 on request Package L-SIM-72-11 L-SIM-72-11 L-SIM-72-11 L-SIM-72-11 Descriptions DRAM module (access time 60 ns) DRAM module (access time 70 ns) DRAM module (access time 60 ns) DRAM module (access time 70 ns)
Semiconductor Group
541
09.94
HYM 321160S/GS-60/-70 1M x 32-Bit
The HYM 321160S/GS-60/-70 is a 4 M Byte DRAM module organized as 1 048 576 words by 32-bit in a 72-pin single-in-line package comprising eight HYB 514400BJ 1M × 4 DRAMs in 300 mil wide SOJ-packages mounted together with eight 0.2 µF ceramic decoupling capacitors on a PC board. The HYM 321160S/GS-60/-70 can also be used as a 2 097 152 words by 16-bits dynamic RAM module by means of connecting DQ0 and DQ16, DQ1 and DQ17, DQ2 and DQ18, …, DQ15 and DQ31, respectively. Each HYB 514400BJ is described in the data sheet and is fully electrically tested and processed according to Siemens standard quality procedure prior to module assembly. After assembly onto the board, a further set of electrical tests is performed. The speed of the module can be detected by the use of four presence detect pins. The common I/O feature on the HYM 321160S/GS-60/-70 dictates the use of early write cycles.
Pin Definitions and Functions Pin No. A0-A9 DQ0-DQ31 CAS0 - CAS3 RAS0, RAS2 WE Function Address Inputs Data Input/Output Column Address Strobe Row Address Strobe Read/Write Input Power (+ 5 V) Ground Presence Detect Pin No Connection
VCC VSS
PD N.C.
Presence Detect Pins -60 PD0 PD1 PD2 PD3 -70
VSS VSS
N.C. N.C.
VSS VSS VSS
N.C.
Semiconductor Group
542
HYM 321160S/GS-60/-70 1M x 32-Bit
Pin Configuration (top view)
Semiconductor Group
543
HYM 321160S/GS-60/-70 1M x 32-Bit
Block Diagram
Semiconductor Group
544
HYM 321160S/GS-60/-70 1M x 32-Bit
Absolute Maximum Ratings Operating temperature range ......................................................................................... 0 to + 70 ˚C Storage temperature range...................................................................................... – 55 to + 125 ˚C Soldering temperature ............................................................................................................ 260 ˚C Soldering time ............................................................................................................................. 10 s Input/output voltage ........................................................................................................ – 1 to + 7 V Power supply voltage...................................................................................................... – 1 to + 7 V Power dissipation................................................................................................................... 6.16 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics 1) TA = 0 to 70 ˚C; VCC = 5 V ± 10 % Parameter Input high voltage Input low voltage Output high voltage (IOUT = – 5 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current (0 V < VIN < 6.5 V, all other pins = 0 V) Output leakage current (DO is disabled, 0 V < VOUT < 5.5 V) Average VCC supply current: -60 version -70 version (RAS, CAS, address cycling, tRC = tRC min.) Standby VCC supply current (RAS = CAS = VIH) Symbol Limit Values min. max. 5.5 0.8 – 0.4 20 10 V V V V µA µA 2.4 – 1.0 2.4 – – 20 – 10 Unit Test Condition – – – – – –
VIH VIL VOH VOL II(L) IO(L) ICC1
– –
880 800
mA mA
2), 3)
ICC2
–
16
mA
–
Average VCC supply current during RAS ICC3 only refresh cycles: -60 version -70 version (RAS cycling, CAS = VIH , tRC = tRC min.)
2)
– –
880 800
mA mA
Sem.