HYM322030S

2M x 32-Bit Dynamic RAM Module HYM 322030S/GS-60/-70 Advanced Information 2 097 152 words by 32-bit organization Fast access and cycle time 60 ns access time 110 ns cycle time (-60 version) 70 ns access time 130 ns cycle time (-70 version) Fast page mode capability 40 ns cycle time (-60 version) 45 ns cycle time (-70 version) Single + 5 V (± 10 %) supply Low power dissipation max. 3300 mW active (-60 version) max. 3025 mW active (-70 version) CMOS – 22 mW standby TTL – 44 mW standby CAS-before-RAS refresh RAS-only-refresh Hidden-refresh 4 decoupling capacitors mounted on substrate All inputs, outputs and clocks fully TTL compatible 72 pin Single in-Line Memory Module (L-SIM-72-9 ) with 20.32 mm (800 mil) height Utilizes four 2M × 8 - DRAMs in 400 mil SOJ-packages 2048 refresh cycles / 32 ms Tin-Lead contact pads (S - version) Gold contact pads (GS - version) Ordering Information Type HYM 322030S-60 HYM 322030S-70 HYM 322030GS-60 HYM 322030GS-70 Ordering Code Q67100-Q976 Q67100-Q977 Q67100-Q2018 Q67100-Q2019 Package L-SIM-72-9 L-SIM-72-9 L-SIM-72-9 L-SIM-72-9 Description DRAM Module (access time 60 ns) DRAM Module (access time 70 ns) DRAM Module (access time 60 ns) DRAM Module (access time 70 ns) Semiconductor Group 561 09.94 HYM 322030S/GS-60/-70 2M × 32-Bit The HYM 322030S/GS-60/-70 is a 8 M Byte DRAM module organized as 2 097 152 words by 32-bit in a 72-pin single-in-line package comprising four HYB 5117800BSJ 2M × 8 DRAMs in 400 ...