HYM72V2005GS-50

2M × 72-Bit EDO-DRAM Module (ECC - Module) 168 pin buffered DIMM Module HYM 72V2005GS-50/-60 168 pin JEDEC Standard, Buffered 8 Byte Dual In-Line Memory Module for PC main memory applications 1 bank 2 M x 72 organisation Optimized for ECC applications Extended Data Out (EDO) Performance: -50 tRAC tCAC tAA tRC tHPC RAS access time CAS access time Access time from address Read/Write cycle time Fast page mode cycle time 50 18 30 84 20 -60 60 20 35 104 25 ns ns ns ns ns Single + 3.3V ± 0.3 V supply CAS-before-RAS refresh, RAS-only refresh Decoupling capacitors mounted on substrate All inputs, outputs and clock fully LVTTL & LVCMOS compatible 4 Byte interleave enabled, Dual Address inputs (A0/B0) Buffered inputs excepts RAS and DQ Parallel Presence Detects Utilizes nine 2M × 8 -DRAMs and BiCMOS buffers/line drivers 2048 refresh cycles / 32 ms with 11 / 10 addressing Gold contact pad Double sided module with 25.35 mm (1000 mil) height Semiconductor Group 1 11.96 HYM72V2005GS-50/-60 2M x 72-ECC Module The HYM 72V2005GS-50/-60 is a 16 MByte DRAM module organized as 2 097 152 words by 72bit in a 168-pin, dual read-out, single-in-line package comprising nine HYB3117805BSJ 2M × 8 EDO DRAMs in 400 mil wide SOJ-28 - packages mounted together with ceramic decoupling capacitors on a PC board. All inputs except RAS and DQ are buffered by using BiCMOS buffers/ line drivers. Each HYB3117805BSJ is described in the data sheet and is fully electrically t...