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IA64250 Dataheets PDF



Part Number IA64250
Manufacturers InnovASIC
Logo InnovASIC
Description Histogram/Hough Transform Processor
Datasheet IA64250 DatasheetIA64250 Datasheet (PDF)

IA64250 Histogram/Hough Transform Processor FEATURES • • • • • Data Sheet As of Production Ver. 01 Histogram and Hough Transform Calculation Four 512 X 9 Look-up Tables Provided to Perform User-defined Point-wise Transformations Real-time Histogram Equalization High Data Rates 512 X 24 Accumulation RAM Pixel Location Function • The IA64250 is a "plug-and-play" drop-in replacement for the original LSI® L64250. This replacement IC has been developed using innovASIC’s MILESTM , or Managed IC Li.

  IA64250   IA64250


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IA64250 Histogram/Hough Transform Processor FEATURES • • • • • Data Sheet As of Production Ver. 01 Histogram and Hough Transform Calculation Four 512 X 9 Look-up Tables Provided to Perform User-defined Point-wise Transformations Real-time Histogram Equalization High Data Rates 512 X 24 Accumulation RAM Pixel Location Function • The IA64250 is a "plug-and-play" drop-in replacement for the original LSI® L64250. This replacement IC has been developed using innovASIC’s MILESTM , or Managed IC Lifetime Extension System, cloning technology. This technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible with the original IC. MILESTM captures the design of a clone so it can be produced even as silicon technology advances. MILESTM also verifies the clone against the original IC so that even the "undocumented features" are duplicated. This data sheet documents all necessary engineering information about the IA64250 including functional and I/O descriptions, electrical characteristics, and applicable timing. Package Pinout for 68 PLCC PACKAGE: 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Copyright © 2000 ENG211001219-01 innovASIC  The End of Obsolescence™ Page 1 of 21 www.innovasic.com Customer Support: 1-888-824-4184 IA64250 Histogram/Hough Transform Processor PIN DESIGNATOR: PIN NAME GND CI.5 CI.4 CI.3 CI.2 CI.1 CI.0 WE REGADR.5 VDD REGADR.4 REGADR.3 REGADR.2 REGADR.1 REGADR.0 VDO.8 VDO.7 GRID # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PIN NAME GND VDD VDO.6 VDO.5 VDO.4 VDO.3 VDO.2 VDO.1 VDO.0 VDD RESET FP GND RY CY RX CX CLK1 GRID # 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Data Sheet As of Production Ver. 01 PIN PIN NAME GRID # NAME GND 35 DO.5 STARTIO 36 DO.6 VDD 37 DO.7 CLK2 38 DO.8 PO 39 DI.0 IODV 40 DI.1 DV 41 DI.2 AT 42 DI.3 GND 43 DI.4 VDD 44 VDD DO.0 45 DI.5 DO.1 46 DI.6 DO.2 47 DI.7 DO.3 48 DI.8 DO.4 49 CI.8 VDD 50 CI.7 GND 51 CI.6 GRID # 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Copyright © 2000 ENG211001219-01 innovASIC  The End of Obsolescence™ Page 2 of 21 www.innovasic.com Customer Support: 1-888-824-4184 IA64250 Histogram/Hough Transform Processor BLOCK DIAGRAM: Figure 1 MOD_RAMDATA SYNC 24 Data Sheet As of Production Ver. 01 AT RAMADDR 9 24 ADDER 24 CLOCK HCLR 2 DV 24 SYNC SHIFT 9 REGADR 6 STARTIO_N RAMDATA 24 ACC RAM 512 X 24 RESETFP SAT SEL 4 9 DO DI 9 CLOCK CONTROLLER LUT 2 CLOCK LUTOUT ADDER 9 10 SHIFT 9 OUT_SEL VDO LUTADDR IODV LUTDATA 9 9 LUT RAM 4 X 512 X 9 CI 9 OUT_SEL 2 RESET 9 CX CLOCK FP COUNTER CLOCK RX X COUNTER X 9 CY CLOCK RY Y COUNTER Y 9 FP CI AT REGADR MARKER MEMORY MODE WE_N Copyright © 2000 ENG211001219-01 innovASIC  The End of Obsolescence™ Page 3 of 21 www.innovasic.com Customer Support: 1-888-824-4184 IA64250 Histogram/Hough Transform Processor Description Data Sheet As of Production Ver. 01 The IA64250 performs three separate tasks, histogram generation, modified Hough transforms, and pixel location. There are three modes of operation for the IA64250: computation, I/O, and initialization. The controller block in the block diagram decodes the instructions and contains the mode registers. After decoding the mode, the controller generates all of the control signals to the rest of the part. These control signals include the addresses and input data for the LUT and ACC RAMs, the select lines for both the output mux and the shifter, and the reset for the FP counter. This block also controls the clearing of the ACC RAM. The ACC RAM stores the video data that is to be output during the I/O mode. This data can be modified, depending on mode, by several methods prior to being output. These methods are described in the computation mode section. The LUT RAM can store up to four different data modifying functions. These functions are used to modify the video data coming in and access the appropriate data in the ACC RAM through the ACC RAM address. This data is then sent out on the DO output. During the initialization mode, the functions to be performed are defined. This is accomplished by setting the values in the mode registers contained in the controller block. During the computation mode, the histogram, Hough transform, or pixel location data is computed. Data equalization also occurs during this mode if desired. The controller block controls the adders and shifters during this mode to ensure correct data manipulation. This is accomplished through the data stored in the mode registers as well as the DV input. The controller block also generates the addresses to both the RAMs. The I/O mode allows data to be transferred to the Accumulation RAM (ACC RAM) and/or to and from the Look Up Table RAM (LUT RAM). The user can also update the marker memory during the I/O mode. The marker memory is used to quickly find poin.


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