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EDI88512CA Dataheets PDF



Part Number EDI88512CA
Manufacturers ETC
Logo ETC
Description 512Kx8 Monolithic SRAM/ SMD 5962-95600
Datasheet EDI88512CA DatasheetEDI88512CA Datasheet (PDF)

EDI88512CA 512Kx8 Monolithic SRAM, SMD 5962-95600 FEATURES ■ Access Times of 15, 17, 20, 25, 35, 45, 55ns ■ Data Retention Function (LPA version) ■ TTL Compatible Inputs and Outputs ■ Fully Static, No Clocks ■ Organized as 512Kx8 ■ Commercial, Industrial and Military Temperature Ranges ■ 32 lead JEDEC Approved Evolutionary Pinout • Ceramic Sidebrazed 600 mil DIP (Package 9) • Ceramic Sidebrazed 400 mil DIP (Package 326) • Ceramic 32 pin Flatpack (Package 344) • Ceramic Thin Flatpack (Package 32.

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EDI88512CA 512Kx8 Monolithic SRAM, SMD 5962-95600 FEATURES ■ Access Times of 15, 17, 20, 25, 35, 45, 55ns ■ Data Retention Function (LPA version) ■ TTL Compatible Inputs and Outputs ■ Fully Static, No Clocks ■ Organized as 512Kx8 ■ Commercial, Industrial and Military Temperature Ranges ■ 32 lead JEDEC Approved Evolutionary Pinout • Ceramic Sidebrazed 600 mil DIP (Package 9) • Ceramic Sidebrazed 400 mil DIP (Package 326) • Ceramic 32 pin Flatpack (Package 344) • Ceramic Thin Flatpack (Package 321) • Ceramic SOJ (Package 140) ■ 36 lead JEDEC Approved Revolutionary Pinout • Ceramic Flatpack (Package 316) • Ceramic SOJ (Package 327) • Ceramic LCC (Package 502) ■ Single +5V (±10%) Supply Operation The EDI88512CA is a 4 megabit Monolithic CMOS Static RAM. The 32 pin DIP pinout adheres to the JEDEC evolutionary standard for the four megabit device. All 32 pin packages are pin for pin upgrades for the single chip enable 128K x 8, the EDI88128CS. Pins 1 and 30 become the higher order addresses. The 36 pin revolutionary pinout also adheres to the JEDEC standard for the four megabit device. The center pin power and ground pins help to reduce noise in high performance systems. The 36 pin pinout also allows the user an upgrade path to the future 2Mx8. A Low Power version with Data Retention (EDI88512LPA) is also available for battery backed applications. Military product is available compliant to Appendix A of MIL-PRF-38535. FIG. 1 PIN CONFIGURATION 36 PIN TOP VIEW A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN DESCRIPTION 32 PIN TOP VIEW 32 VCC 31 A15 30 A17 29 WE 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CS 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3 A -18 I/O 0-7 Data Inputs/Outputs A0-18 WE CS OE VCC V SS NC Address Inputs Write Enables Chip Selects Output Enable Power (+5V ±10%) Ground Not Connected BLOCK DIAGRAM Memory Array Address Buffer Address Decoder I/O Circuits I/O -7 WE CS OE Aug. 2002 Rev. 9 1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI88512CA ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Operating Temperature TA (Ambient) Commercial Industrial Military Storage Temperature, Plastic Power Dissipation Output Current Junction Temperature, TJ -0.5 to 7.0 0 to +70 -40 to +85 -55 to +125 -65 to +150 1.5 20 175 Unit V °C °C °C °C W mA °C OE X H L X CS H L L L WE X H H L TRUTH TABLE Mode Output Standby High Z Output Deselect High Z Read Data Out Write Data In Power Icc 2 , Icc 3 Icc 1 Icc 1 Icc 1 RECOMMENDED OPERATING CONDITIONS Parameter Symbol Supply Voltage VCC Supply Voltage V SS Input High Voltage VIH Input Low Voltage VIL Min 4.5 0 2.2 -0.3 Typ 5.0 0 — — Max 5.5 0 3.0 +0.8 Unit V V V V NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA = +25°C) Parameter Symbol Condition Max Unit Address Lines CI VIN = Vcc or Vss, f = 1.0MHz 12 pF Data Lines CO VOUT = Vcc or Vss, f = 1.0MHz 14 pF These parameters are sampled, not 100% tested. DC CHARACTERISTICS (VCC = 5V, TA = -55°C TO +125°C) Parameter Input Leakage Current Output Leakage Current Operating Power Supply Current Standby (TTL) Power Supply Current Full Standby Power Supply Current Output Low Voltage Output High Voltage Symbol I LI I LO I CC 1 I CC 2 I CC 3 VOL VOH Conditions VIN = 0V to VCC VI/O = 0V to VCC WE, CS = VIL, II/O = 0mA, Min Cycle CS ³ VIH, VIN £ VIL, VIN ³ VIH CS ³ VCC -0.2V VIN ³ Vcc -0.2V or VIN £ 0.2V IOL = 8.0mA IOH = -4.0mA Min -10 -10 — — — — — — 2.4 Max 10 10 250 225 60 25 20 0.4 — Units µA µA mA mA mA mA mA V V (17ns) (20 -55ns) CA LPA NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V AC TEST CONDITIONS Figure 1 Vcc Figure 2 Vcc 480Ω 480Ω Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load VSS to 3.0V 5ns 1.5V Figure 1 NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2) Q 255Ω 30pF Q 255Ω 5pF White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 2 EDI88512CA AC CHARACTERISTICS – READ CYCLE (VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C) Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) Symbol JEDEC Alt. tAVAV t RC tAVQV t AA t ELQV t ACS t ELQX t CLZ t EHQZ t CHZ tAVQX t OH tGLQV t OE tGLQX tOLZ tGHQZ t OHZ 15ns Min Max 15 15 15 2 0 7 0 8 0 0 7 17ns Min Max 17 17 17 3 0 7 0 8 0 0 7 20ns Min Max 20 20 20 3 0 8 0 10 0 0 8 25ns 35ns 45ns 55ns Min Max Min Max Min Max.


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