PDI1394P22BD

INTEGRATED CIRCUITS PDI1394P22 3-port physical layer interface Objective specification 1999 Jul 09 Philips Semiconductors Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 1.0 FEATURES Fully supports provisions of IEEE 1394–1995 Standard for high performance serial bus and the P1394a supplement (Version 2.0)1 Supports extended bias-handshake time for enhanced interoperability with camcorders Full P1394a support includes: – Connection debounce – Arbitrated short reset – Multispeed concatenation – Arbitration acceleration – Fly-by concatenation – Port disable/suspend/resume Interface to link-layer controller supports low-cost bus-holder isolation and optional Annex J electrical isolation Data interface to link-layer controller through 2/4/8 parallel lines at 49.152 MHz Low-cost 24.576 MHz crystal provides transmit, receive data at 100/200/400 Mbits/s, and link-layer controller clock at 49.152 MHz Provides three 1394a fully-compliant cable ports at 100/200/400 Megabits per second (Mbits/s) Does not require external filter capacitors for PLL Interoperable with link-layer controllers using 3.3 V and 5 V supplies Fully compliant with Open HCI requirements Cable ports monitor line conditions for active connection to remote node. Interoperable with other Physical Layers (PHYs) using 3.3 V and 5 V supplies Power down features to conserve energy in battery-powered applications include: – Automatic devic...