PDI1394P23

INTEGRATED CIRCUITS PDI1394P23 2-port/1-port 400 Mbps physical layer interface Preliminary data Supersedes data of 2001 Jul 18 2001 Sep 06 Philips Semiconductors Philips Semiconductors Preliminary data 2-port/1-port 400 Mbps physical layer interface PDI1394P23 1.0 FEATURES Fully supports provisions of IEEE 1394–1995 Standard for high performance serial bus and the P1394a–2000 Standard.1 Interoperable with link-layer controllers using 3.3 V and 5 V supplies Fully interoperable with Firewire™ and i.LINK™ implementations of the IEEE 1394 Standard.2 Interoperable with other Physical Layers (PHYs) using 3.3 V and 5 V supplies Full P1394a support includes: – Connection debounce – Arbitrated short reset – Multispeed concatenation – Arbitration acceleration – Fly-by concatenation – Port disable/suspend/resume Node power class information signaling for system power management Cable power presence monitoring Power down features to conserve energy in battery-powered applications include: – Automatic device power down during suspend – Device power down terminal – Link interface disable via LPS – Inactive ports powered-down Provides two 1394a fully-compliant cable ports at 100/200/400 Mbps. Fully compliant with Open HCI requirements Interface to link-layer controller supports both low-cost bus-holder isolation and optional Annex J electrical isolation While unpowered and connected to the bus, will not drive TPBIAS on a connected port, even if recei...