PDI1394P25

INTEGRATED CIRCUITS PDI1394P25 1-port 400 Mbps physical layer interface Preliminary data Supersedes data of 2001 Jul 18 2001 Sep 06 Philips Semiconductors Philips Semiconductors Preliminary data 1-port 400 Mbps physical layer interface PDI1394P25 1.0 FEATURES Fully supports provisions of IEEE 1394–1995 Standard for high performance serial bus and the P1394a–2000 Standard1 Supports extended bias-handshake time for enhanced interoperability with camcorders Fully interoperable with Firewire™ and i.LINK™ implementations of the IEEE 1394 Standard.2 Interface to link-layer controller supports both low-cost bus-holder isolation and optional Annex J electrical isolation Full P1394a support includes: – Connection debounce – Arbitrated short reset – Multispeed concatenation – Arbitration acceleration – Fly-by concatenation – Port disable/suspend/resume Data interface to link-layer controller through 2/4/8 parallel lines at 49.152 MHz Low-cost 24.576 MHz crystal provides transmit, receive data at 100/200/400 Mbps, and link-layer controller clock at 49.152 MHz Does not require external filter capacitors for PLL Interoperable with link-layer controllers using 3.3 V and 5 V supplies Provides one 1394a fully-compliant cable port at 100/200/400 Mbps. Can be used as a one port PHY without the use of any extra external components Interoperable with other Physical Layers (PHYs) using 3.3 V and 5 V supplies Fully compliant with Open HCI requirements Ca...