M50FW040

M50FW040 4 Mbit (512Kb x8, Uniform Block) 3V Supply Firmware Hub Flash Memory s SUPPLY VOLTAGE – VCC = 3V to 3.6V for Program, Erase and Read Operations s – VPP = 12V for Fast Erase (optional) TWO INTERFACES – Firmware Hub (FWH) Interface for embedded operation with PC Chipsets. – Address/Address Multiplexed (A/A Mux) Interface for programming equipment compatibility. s FIRMWARE HUB (FWH) HARDWARE INTERFACE MODE – 5 Signal Communication Interface supporting Read and Write Operations – Hardware Write Protect Pins for Block Protection – Register Based Read and Write Protection – 5 Additional General Purpose Inputs for platform design flexibility – Synchronized with 33MHz PCI clock PLCC32 (K) TSOP40 (N) 10 x 20mm Figure 1. Logic Diagram (FWH Interface) VCC VPP 4 ID0-ID3 5 FGPI0FGPI4 FWH4 CLK IC RP INIT M50FW040 WP TBL 4 FWH0FWH3 s s s PROGRAMMING TIME: 10µs typical 8 UNIFORM 64 Kbyte MEMORY BLOCKS PROGRAM/ERASE CONTROLLER – Embedded Byte Program and Block Erase algorithms – Status Register Bits s PROGRAM and ERASE SUSPEND – Read other Blocks during Program/Erase Suspend – Program other Blocks during Erase Suspend s s FOR USE in PC BIOS APPLICATIONS ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: 2Ch VSS AI03623 March 2002 1/32 M50FW040 Figure 2. Logic Diagram (A/A Mux Interface) DESCRIPTION The M50FW040 is a 4 Mbit (512Kb x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (...