M50LPW116

M50LPW116 16 Mbit (2Mb x8, Boot Block) 3V Supply Low Pin Count Flash Memory PRELIMINARY DATA s SUPPLY VOLTAGE – VCC = 3V to 3.6V for Program, Erase and Read Operations s – VPP = 12V for Fast Program and Fast Erase TWO INTERFACES – Low Pin Count (LPC) Standard Interface for embedded operation with PC Chipsets. – Address/Address Multiplexed (A/A Mux) Interface for programming equipment compatibility. s LOW PIN COUNT (LPC) HARDWARE INTERFACE MODE – 5 Signal Communication Interface supporting Read and Write Operations – Hardware Write Protect Pins for Block Protection – Register Based Read and Write Protection – 5 Additional General Purpose Inputs for platform design flexibility – Synchronized with 33 MHz PCI clock TSOP40 (N) 10 x 20mm Figure 1. Logic Diagram (LPC Interface) VCC VPP 4 ID0-ID3 5 GPI0GPI4 LFRAME CLK IC RP INIT M50LPW116 WP TBL 4 LAD0LAD3 s BYTE PROGRAMMING TIME – Single Byte Mode: 10µs (typical) – Quadruple Byte Mode: 2.5µs (typical) s 50 MEMORY BLOCKS – 1 Boot Block – 18 Parameter and 31 Main Blocks s PROGRAM/ERASE CONTROLLER – Embedded Byte Program and Block/Chip Erase algorithms – Status Register Bits s s PROGRAM and ERASE SUSPEND ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: 30h VSS AI05466 February 2003 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/36 M50LPW116 Figure 2. Logic Diagram (A/A Mux Interface) DESCRIPTION The M50LPW116 is...