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PDSP1601A Dataheets PDF



Part Number PDSP1601A
Manufacturers Mitel Networks Corporation
Logo Mitel Networks Corporation
Description ALU and Barrel Shifter
Datasheet PDSP1601A DatasheetPDSP1601A Datasheet (PDF)

PDSP1601/PDSP1601A ALU and Barrel Shifter Supersedes version DS3705 - 2.3 September 1996 DS3705 - 3.0 November 1998 PDSP1601/PDSP1601A The PDSP1601 is a high performance 16-bit arithmetic logic unit with an independent on-chip 16-bit barrel shifter. The PDSP1601A has two operating modes giving 20MHz or 10MHz register-to-register transfer rates. The PDSP1601 supports Multicycle multiprecision operation. This allows a single device to operate at 20MHz for 16-bit fields, 10MHz for 32-bit fields a.

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PDSP1601/PDSP1601A ALU and Barrel Shifter Supersedes version DS3705 - 2.3 September 1996 DS3705 - 3.0 November 1998 PDSP1601/PDSP1601A The PDSP1601 is a high performance 16-bit arithmetic logic unit with an independent on-chip 16-bit barrel shifter. The PDSP1601A has two operating modes giving 20MHz or 10MHz register-to-register transfer rates. The PDSP1601 supports Multicycle multiprecision operation. This allows a single device to operate at 20MHz for 16-bit fields, 10MHz for 32-bit fields and 5MHz for 64-bit fields. The PDSP1601 can also be cascaded to produce wider words at the 20MHz rate using the Carry Out and Carry In pins. The Barrel Shifter is also capable of extension, for example the PDSP1601 can used to select a 16-bit field from a 32-bit input in 100ns. PIN 1A INDEX MARK ON TOP SURFACE A B C D E F G H J K L 11 10 9 8 7 6 5 4 3 2 1 AC84 FEATURES s s s s s s s s s 16-bit, 32 instruction 20MHz ALU 16-bit, 20MHz Logical, Arithmetic or Barrel Shifter Independent ALU and Shifter Operation 4 x 16-bit On Chip Scratchpad Registers Multiprecision Operation; e.g. 200ns 64-bit Accumulate Three Port Structure with Three Internal Feedback Paths Eliminates I/O Bottlenecks Block Floating Point Support 300mW Maximum Power Dissipation 84-pin Pin Grid Array or 84 Contact LCC Packages or 100 pin Ceramic Quad Flat Pack GC100 Fig.1 Pin connections - bottom view APPLICATIONS ORDERING INFORMATION PDSP1601 MC GGCR PDSP1601A BO AC N.B 10MHz MIL883 Screened QFP package 20MHz Industrial - PGA package s s s s s Digital Signal Processing Array Processing Graphics Database Addressing High Speed Arithmetic Processors ASSOCIATED PRODUCTS PDSP16112 PDSP16116 PDSP16318 PDSP16330 Complex Multiplier 16 x 16 Complex Multiplier Complex Accumulator Pythagoras Processor Further details of the Military grade part are available in a separate datasheet (DS3763) 1 PDSP1601/PDSP1601A PIN DESCRIPTION AC pin Function AC pin Function AC pin Function AC pin Function C6 A6 A5 B5 C5 A4 B4 A3 A2 B3 A1 B2 C2 B1 C1 D2 D1 E3 E2 E1 F1 IA4 MSB MSS B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 CEB CLK F3 G3 G1 G2 F1 H1 H2 J1 K1 J2 L1 K2 K3 L2 L3 K4 L4 J5 K5 L5 K6 GND MSA0 MSA1 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CEA MSC J6 J7 L7 K7 L6 L8 K8 L9 L10 K9 L11 K10 J10 K11 J11 H10 H11 F10 G10 G11 G9 IS0 IS1 IS2 IS3 SV0 SV1 SV2 SV3 SVOE RS0 RS1 VCC RS2 C0 C1 C2 C3 C4 C5 C6 C7 F9 F11 E11 E10 E9 D11 D10 C11 B11 C10 A11 B10 B9 A10 A9 B8 A8 B6 B7 A7 C7 GND C8 C9 C10 C11 C12 C13 C14 C15 OE BFP VCC CO RA0 RA1 RA2 CI IA0 IA1 IA2 IA3 GC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SIG N/C N/C N/C N/C VCC C0 RA0 RA1 RA2 CI IA0 IA1 IA2 IA3 IA4 MSB MSS B15 B14 B13 B12 B11 B10 B9 B8 GC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SIG N/C N/C N/C N/C B7 B6 B5 B4 B3 B2 B1 B0 CEB CLK GND MSA0 MSA1 A15 A14 A13 A12 A11 A10 A9 A8 GC 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 SIG N/C N/C N/C N/C A7 A6 A5 A4 A3 A2 A1 A0 CEA MSC IS0 IS1 IS2 IS3 SV0 SV1 SV2 SV3 SVOE RS0 RS1 GC 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 SIG N/C N/C N/C N/C VCC RS2 C0 C1 C2 C3 C4 C5 C6 C7 GND C8 C9 C10 C11 C12 C13 C14 C15 OE BFP N/C = not connected - leave open circuit All GND and VDD pin must be used 2 PDSP1601/PDSP1601A PIN DESCRIPTIONS Symbol MSB MSS B15 - B0 CEB CLK MSA0 - MSA1 A15 - A0 CEA MSC IS0 - IS3 SV0 - SV3 Description ALU B-input multiplexer select control.1 This input is latched internally on the rising edge of CLK. Shifter Input multiplexer select control.1 This input is latched internally on the rising edge of CLK. B Port data input. Data presented to this port is latched into the input register on the rising edge of CLK. B15 is the MSB. Clock enable, B Port input register. When low the clock to this register is enabled. Common clock to all internal registered elements. change on the rising edge of CLK. All registers are loaded, and outputs ALU A-input multiplexer select control.1 These inputs are latched internally on the rising edge of CLK. A Port data input. Data presented to this port is latched into the input register on the rising edge of CLK. A15 is the MSB. Clock enable, A Port input register. When low the clock to this register is enabled. C-Port multiplexer select control.1 This input is latched internally on the rising edge of CLK. Instruction inputs to Barrel Shifter, IS3 = MSB.1 These inputs are latched internally on the rising edge of CLK. Shift Value I/O Port. This port is used as an input when shift values are supplied from external sources, and as an output when Normalise operations are invoked. The I/O functions are determined by the IS0 - IS3 instruction inputs, and by the SVOE control. The shift value is latched internally on the rising edge of CLK. SV Output enable. When high the SV port can only operate as an input. When low the SV port can act as an input or as an output, according to the IS0 .


PDSP1601-MC PDSP1601A PDSP1601AB0


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