PDSP16256

PDSP16256/A Programmable FIR Filter DS3709 Issue 7.1 June 1999 Features q q q Ordering Information Commercial (0°C to 170°C) PDSP16256A/C0/AC 25MHz, PGA package Industrial (240°C to 185°C) PDSP16256 B0/AC 20MHz, PGA package PDSP16256 B0/GC 20MHz, QFP package Military (255°C to 1125°C) PDSP16256 MC/AC1R 20MHz, MIL-STD-883* (latest revision), PGA package PDSP16256 MC/GC1R 20MHz, MIL-STD-883* (latest revision), QFP package *See notes following Electrical Characteristics for further information on MIL-STD-883 screening q q q q Sixteen MACs in a Single Device Basic Mode is 16-Tap Filter at up to 25MHz Sample Rates Programmable to give up to 128 Taps with Sampling Rates Proportionally Reducing to 3·125MHz 16-bit Data and 32-bit Accumulators Can be configured as One Long Filter or Two Half-Length Filters Decimate-by-two Option will Double the Filter Length Coefficients supplied from Host System or local EPROM Applications q Associated Products PDSP16350 I/Q Splitter/NCO PDSP16510A FFT Processor High Performance Digital Filters Description The PDSP16256 contains sixteen multiplier accumulators, which can be multi cycled to provide from 16 to 128 stages of digital filtering. Input data and coefficients are both represented by 16-bit two’s complement numbers with coefficients converted internally to 12 bits and the results being accumulated up to 32 bits. In 16-tap mode the device samples data at the system clock rate of up to 25MHz. If a lower sample rate is acceptable then th...