M54HC640

M54/74HC245/640/643 M54/74HC245/640/643 OCTAL BUS TRANSCEIVER (3-STATE): HC245 NON INVERTING HC640 INVERTING, HC643 INVERTING/NON INVERTING . . . . . . . . HIGH SPEED tPD = 10 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION o ICC = 4 µA (MAX.) at TA = 25 C HIGH NOISE IMMUNITY VNIH = VINL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 6 mA (MIN) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS245/640/643 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HCXXXF1R M74HCXXXM1R M74HCXXXB1R M74HCXXXC1R DESCRIPTION The M54/74HC245, HC640 and HC643 utilise silicon gate C2MOS technology to achive operating speeds equivalent to LSTTL devices. Along with the low power dissipation and high noise 2 immunity of standards C MOS integrated circuit, it possesses the capability to drive 15 LSTTL loads. These IC’s are intended for two-way asynchronous communication between data buses, and the direction of data trasmission is determined by DIR input. The enable input (G) can be used to disable the device so that the buses are effectively isolated. PIN CONNECTION (top view) HC245 HC640 HC643 All input are equipped with protection circuits against static discharge and transient discharge and transient excess voltage. IT IS PROHIBITED TO APPLY A SIGNAL TO A BUS TERMINAL WHEN IT IS IN OUTPUT MODE AND WHEN A BUS...