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PDSP16330MC Dataheets PDF



Part Number PDSP16330MC
Manufacturers Mitel Networks Corporation
Logo Mitel Networks Corporation
Description Pythagoras Processor
Datasheet PDSP16330MC DatasheetPDSP16330MC Datasheet (PDF)

PDSP16330 MC Pythagoras Processor Supersedes October 1995 version, DS3240 - 2.1 DS3240 - 3.1 November 1998 The PDSP16330 is a high speed digital CMOS IC that converts Cartesian data (Real and Imaginary) into Polar form (Magnitude and Phase), at rates up to 10MHz. Cartesian 16+16 bit 2's complement or Sign-Magnitude data is converted into 16 bit Phase format. The Magnitude output may be scaled in amplitude by powers of 2. The Phase output represents a full 2 x π field to eliminate phase ambiguit.

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PDSP16330 MC Pythagoras Processor Supersedes October 1995 version, DS3240 - 2.1 DS3240 - 3.1 November 1998 The PDSP16330 is a high speed digital CMOS IC that converts Cartesian data (Real and Imaginary) into Polar form (Magnitude and Phase), at rates up to 10MHz. Cartesian 16+16 bit 2's complement or Sign-Magnitude data is converted into 16 bit Phase format. The Magnitude output may be scaled in amplitude by powers of 2. The Phase output represents a full 2 x π field to eliminate phase ambiguities. Polyimide is used as an inter-layer dielectric and as glassivation. GC100 FEATURES 10MHz Cartesian to Polar Conversion 16-Bit Cartesian Inputs 16-Bit Magnitude Output 12-Bit Phase Output 2’s Complement or Sign-Magnitude Input Formats Three-state Outputs and Independent Data Enables Simplify System Interfacing Magnitude Scaling Facility with Overflow Flag Less than 400 mW Power Dissipation at 10MHz 100 pin CQFP Package Fig.1 Pin connections - QFP Package Rev Date A B C D FEB 1992 MAR 1993 OCT 1995 NOV 1998 ASSOCIATED PRODUCTS PDSP16112 PDSP16116 PDSP16318 PDSP16350 PDSP16510A 16 X 12 Complex Multiplier 16 X 16 Complex Multiplier Complex Accumulator I/Q Splitter and NCO Stand Alone FFT Processor APPLICATIONS Digital Signal Processing Digital Radio Radar Processing Sonar Processing Robotics ORDERING INFORMATION PDSP16330/MC/GC1R (10MHz - QFP Package, MIL-STD-883 Screening) X15:0 Y15:0 CEX CEY 16 16 16 π FORM MAGNITUDE 15 X 2 30 SIGN SIGN MAGNITUDE 15 Y 2 30 SIGN X SIGN Y X>Y Y/X 9 /4 ARCTAN ROM 9 + 32 2 2 X +Y 16 S0 ROTATE 12 SHIFT S1 2 OEM OEP M15:0 OVR P11:0 Fig.2 Block diagram PDSP16330 MC FUNCTIONAL DESCRIPTION The PDSP16330 converts incoming Cartesian Data into the equivalent Polar Values. The device accepts new 16 + 16 bit complex data every cycle, and delivers a 16 bit + 12 bit Polar equivalent after 24 clock cycles.The input data can be in 2s’ Complement or Sign Magnitude format selected via the FORM input. The output is in a magnitude format for both the Magnitude output and the Phase. Phase data is zero for data with a zero Y input and positive X, and is 400 hex for zero X data and positive Y, is 800 hex for zero Y data and negative X, and is C00 hex for zero X and negative Y. The LSB weighting (bit 0) is 2 x π/4096 radians. The 16 bit Magnitude result may be scaled by shifting one, two, or three places in the more significant direction, effectively multiplying the Magnitude result by 2,4 or 8 respectively. Any of these shifts can under certain conditions cause an invalid result to be output from the device. Under these circumstances the OVR output will become active. The PDSP16330 has independent clock enables and three state output controls for all ports. S1-0 These inputs select the scaling factor to be applied to the Magnitude output. They are latched by the rising edge of CLK and determine the scaling of the output in the cycle after they are loaded into the device. The scale factor applied is determined by .


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