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K4E170411D, K4E160411D K4E170412D, K4E160412D
CMOS DRAM
4M x 4Bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 4.194,304 x 4 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K Ref.), access time (-50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx4 EDO DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as main memory unit for high level computer, microcomputer and personal computer.
FEATURES
• Part Identification - K4E170411D-B(F) (5V, 4K Ref.) - K4E160411D-B(F) (5V, 2K Ref.) - K4E170412D-B(F) (3.3V, 4K Ref.) - K4E160412D-B(F) (3.3V, 2K Ref.)
• Extended Data Out Mode operation (Fast Page Mode with Extended Data Out) • CAS-before-RAS refresh capability • RAS-only and Hidden refresh capability • Self-refresh capability (L-ver only) • Fast parallel test mode capability • TTL(5V)/LVTTL(3.3V) compatible inputs and outputs • Early Write or output enable controlled write Unit : mW • JEDEC Standard pinout • Available in Plastic SOJ and TSOP(II) packages 2K 605 550 • Single +5V±10% power supply (5V product) • Single +3.3V±0.3V power supply (3.3V product)
• Active Power Dissipation 3.3V 4K -50 -60 324 288 2K 396 360 4K 495 440 5V
Speed
FUNCTIONAL BLOCK DIAGRAM
• Refresh Cycles Part NO. K4E170411D K4E170412D K4E160411D K4E160412D VCC 5V 3.3V 5V 3.3V 2K 32ms
Refresh Control Refresh Counter Memory Array 4,194,304 x4 Cells
Refresh Refresh period cycle Normal L-ver 4K 64ms 128ms
RAS CAS W
Control Clocks
VBB Generator
Vcc Vss
Data in Refresh Timer Row Decoder Sense Amps & I/O Buffer
DQ0 to DQ3
• Performance Range Speed -50 -60
tRAC
50ns 60ns
tCAC
15ns 17ns
tRC
84ns 104ns
tHPC
20ns 25ns
Remark 5V/3.3V 5V/3.3V
A0-A11 (A0 - A10) *1 A0 - A9 (A0 - A10) *1
Row Address Buffer Col. Address Buffer Column Decoder
Data out Buffer OE
Note) *1 : 2K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
K4E170411D, K4E160411D K4E170412D, K4E160412D
CMOS DRAM
PIN CONFIGURATION (Top Views)
• K4E17(6)0411(2)D-B
• K4E17(6)0411(2)D-F
VCC DQ0 DQ1 W RAS *A11(N.C)
1 2 3 4 5 6
24 23 22 21 20 19
VSS DQ3 DQ2 CAS OE A9
VCC DQ0 DQ1 W RAS *A11(N.C)
1 2 3 4 5 6
24 23 22 21 20 19
VSS DQ3 DQ2 CAS OE A9
A10 A0 A1 A2 A3 VCC
7 8 9 10 11 12
18 17 16 15 14 13
A8 A7 A6 A5 A4 VSS
A10 A0 A1 A2 A3 VCC
7 8 9 10 11 12
18 17 16 15 14 13
A8 A7 A6 A5 A4 VSS
*A11 is N.C for K4E160411(2)D(5V/3.3V, 2K Ref. product) B : 300mil 26(24) SOJ F: 300mil 26(24) TSOP II
Pin Name A0 - A11 .