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KB2514 Dataheets PDF



Part Number KB2514
Manufacturers Samsung
Logo Samsung
Description VIDEO AMP MERGED OSD PROCESSOR
Datasheet KB2514 DatasheetKB2514 Datasheet (PDF)

JAN. 2000 Ver 0.1 DATA SHEET KB2514 Preliminary Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS KB2514 VIDEO AMP MERGED OSD PROCESSOR The KB2514 is a very high frequency video amplifier & wide range OSD processor 1 chip system with I2C Bus control used in monitors. It contains 3 matched R/G/B video amplifiers with OSD processor and provides flexible interfacing to I2C Bus controlled adjustment systems. 32-DIP-600A FUNCTIONS • • • • • • R/G/B video amplifier OSD processor I2C bus co.

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JAN. 2000 Ver 0.1 DATA SHEET KB2514 Preliminary Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS KB2514 VIDEO AMP MERGED OSD PROCESSOR The KB2514 is a very high frequency video amplifier & wide range OSD processor 1 chip system with I2C Bus control used in monitors. It contains 3 matched R/G/B video amplifiers with OSD processor and provides flexible interfacing to I2C Bus controlled adjustment systems. 32-DIP-600A FUNCTIONS • • • • • • R/G/B video amplifier OSD processor I2C bus control Cut-off brightness control R/G/B sub contrast/cut-off control Half tone ORDERING INFORMATION Device KB2514 Package 32-DIP-600A Operating Temperature -20 °C − +75 °C FEATURES VIDEO AMP PART • • 3-channel R/G/B video amplifier, 150MHz @f-3dB I2C bus control items - Contrast control: -38dB - Sub contrast control for each channel: -12dB - Brightness control - OSD contrast control: -38dB - Cut-off brightness control (AC coupling) - Cut-off control for each channel (AC coupling) - Switch registers for SBLK and video half tone and CLP/BLK polarity selection and INT/EXT CLP selection Built in ABL (automatic beam limitation) Built in video input clamp, BRT clamp Built in video half tone (3mode) function on OSD pictures Capable of 8.0Vp-p output swing Improvement of rise & fall time (2.2ns) Cut-off brightness control Built in blank gate with spot killer Clamp pulse generator OSD intensity BLK, CLP polarity selection Clamp gate with anti OSD sagging • • • • • OSD PART • • • • • • • Built in 1K-byte SRAM 256 ROM fonts (each font consists of 12 × 18 dots.) Full screen memory architecture Wide range PLL available (15kHz ~ 90kHz, Reference 800 X 600) Programmable vertical height of character Programmable vertical and horizontal positioning Character color selection up to 16 different colors (in a units of character) Programmable background color (up to 16 colors) Character blinking and shadowing Character scrolling 72MHz pixel frequency from on-chip PLL (Reference 800 X 600) Full white pattern generation function • • • • • • • • • • • 1 KB2514 Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS BLOCK DIAGRAM 6 VDDA VSSA VDD 31 9 ROM (448 x 18 x 12) ROM 16 VSS 28 Font Data 12 (480 x 16) ROM Address Ctrl Font Data Receiver RAM Data Ctrl Data 16 CLK Frame Ctrl H_Pulse V_Pulse ROM Ctrl 2 32 HFLB VCC3 11 Output Stage GND3 9 Display Display Ctrl Controller Control Register OSD PLL 1 3 VFLB VCO_IN_P VREF1 4 R/G/B OSD H/V/CLK Ctrl H/V/CLK Ctrl FBLK Intensity Timing Controller Frame Ctrl ROM Ctrl Latches I C bus decoder D/A 2 30 SDA 29 SCL Band Gap.Ref VREF 5 Multi (3 mode) Half Tone RGB OSD FBL BLK INTE HT DET. CLP BLK Int Clamp Pulse Gen. R cut off G cut off V/I V/I V/I 27 RCT 26 GCT 25 BCT HFLB B cut off ABL CONT_CAP 8 7 ABL 10 CLP_IN RIN 12 GND1 15 Video Input Clamp CLP Video Half Tone SW FBLK I2C Sub Cont. Control I2C Video Contrast + Sub Cont. Control Amp Out BLK 24 R OUT 22 VCC2 R OSD OSD Input Cilp. HT DET. OSD Half Tone SW FBLK I2C OSD Cont. Control I2C Birght Control I2C Cont. Cntl I2C CLP 23 R CLP 19 GND2 20 G CLP VCC1 13 GIN 14 G-CHANNEL G OSD CLP HT DET. FBLK I2C CLP BLK 21 G OUT 17 B CLP BIN 16 B OSD CLP HT DET. FBLK B-CHANNEL 18 B OUT I2C CLP BLK Figure 1. Functional Block Diagram 2 Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS KB2514 PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 VFLB VSSA VCO_IN_P VREF1 VREF VDDA CONT_CAP ABL_IN GND3 HFLB 32 VDD 31 SDA 30 SCL 29 VSS 28 RCT 27 GCT 26 KB2514 KB2502 BCT 25 ROUT 24 RCLP 23 VCC2 22 GOUT 21 GCLP 20 GND2 19 BOUT 18 BCLP 17 10 CLP_IN 11 VCC3 12 RIN 13 VCC1 14 GIN 15 GND1 16 BIN Figure 2. Pin Configuration 3 KB2514 Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS Table 1. Pin Configuration Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol VFLB VSSA VCO_IN_P VREF1 VREF VDDA CONT_CAP ABL GND3 CLP_IN VCC3 RIN VCC1 GIN GND1 BIN BCLP BOUT GND2 GCLP GOUT VCC2 RCLP ROUT BCT GCT RCT VSS SCL SDA VDD HFLB I/O I I O O I I I O O O I I/O I Vertical flyback signal Ground (PLL part) This voltage is generated at the external loop filter and goes into the input stage of the VCO. Charge pump output PLL regulator filter +5V supply voltage for PLL part Contrast control for AMP part Auto beam limit. Ground for video AMP part(for AMP control) Video clamp pulse input +12V supply voltage for video AMP part(for AMP control) Video signal input (red) +12V supply voltage for video AMP(for main video signal process) Video signal input (green) Ground for video AMP part(for main video signal process) Video signal input (blue) B output clamp cap Video signal output (blue) Ground for video AMP part(for video output drive) G output clamp cap Video signal output (green) +12V supply voltage for video AMP part(for video output drive) R output clamp cap Video signal output (red) B cut-off output G cut-off output R cut-off output Ground for digital part Serial clock (I2C) Serial .


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