Document
PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
INTRODUCTION
The KB8821/22/23 are high performance dual frequency synthesizers with integrated prescalers designed for RF operation up to 1.2GHz/2.0GHz/2.5GHz and IF operation up to 520MHz. The KB8821/22/23 contain dual-modulus prescalers. The RF synthesizer adopts a 64/65 or an 128/129 prescaler(32/33 or 64/65 for the KB8823) and the IF synthesizer adopts an 8/9 or a 16/17 prescaler. Using a proprietary digital phase-locked-loop technique, the KB8821/22/23 have linear phase detector characteristic and can be used for very stable, low noise local oscillator signal. Supply voltage can range from 2.7V to 4.0V. The KB8821/22/ 23 are now available in a 20-TSSOP/24-QFN package.
20-TSSOP-225
KB8821/22/23
ORDERING INFORMATION
Device KB8821/22/23 KB8821/22/23 Package 24-QFN* Tem. Range -40 ~ +85°C 20-TSSOP-225 -40 ~ +85°C
FEATURES
• Very low current consumption(8821:3.5mA, 22:4.5mA, 23:5.5mA) • Operating voltage range : 2.7 ~ 4.0V • Selectable power saving mode(Icc=1uA typical @3V) • Dual modulus prescaler :
KB8821/22 KB8823 KB8821/22/23 (RF) 64/65 or 128/129 (RF) 32/33 or 64/65 (IF) 8/9 or 16/17
* QFN : Quad Flat Non-leaded(see Addendum).
APPLICATIONS
• Cellular telephone systems : KB8821 • Portable wireless communications : KB8822 (PCS/PCN, cordless) • Wireless Local Area Networks (W-LANs) : KB8823 • Other wireless communication systems
• Programmability via serial bus interface • No dead-zone PFD • Variable charge pump output current • High speed lock mode
BLOCK DIAGRAM
finRF finRF + RF Prescaler RF N Counter RF Phase Detector RF LD CLOCK LE DATA Serial Data Control foLD Data Out Multiplexer foLD RF Charge Pump CPoRF
RF R Counter OSCin IF R Counter finIF finIF + IF Prescaler IF N Counter IF Phase Detector
IF LD IF Charge Pump CPoIF
Figure 1. BLOCK DIAGRAM
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
BLOCK DIAGRAM- Continued
KB8821/22/23
VDD1 1
RF LD
foLD Data Out Multiplexer
IF LD
20 VDD2
VP1 2
RF Charge Pump
RF Phase Detector
IF Phase Detector
IF Charge Pump
19 VP2
CPoRF 3 RF Prescaler GND 4 + finRF 5 – Prescaler Control RF Programmable Counter IF Programmable Counter Prescaler Control – + IF Prescaler
18 CPoIF
17 GND
16 finIF
finRF 6 RF N-Latch GND 7 IF N-Latch 20-bit Shift Register RF R-Latch IF R-Latch 2-bit Control
15 finIF
14 GND
OSCin 8
13 LE
GND 9
RF Reference Counter
IF Reference Counter
12 DATA
foLD 10
11 CLOCK
Figure 2. Detailed block diagram
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
PIN CONFIGURATION
KB8821/22/23
VDD1 1 Vp1 2 CPoRF 3 GND 4 (Digital) finRF 5
20 VDD2 19 Vp2 18 CPoIF 17 GND (Digital) 16 finIF
KB8821 KB8822
finRF 6
15 finIF
KB8823
GND 7 (Analog) OSCin 8 GND 9 (Digital) foLD 10 20-TSSOP
Top View
14 GND (Analog) 13 LE 12 DATA 11 CLOCK
20-Lead(0.173 Wide) Thin Shrink Small Outline Package(20-TSSOP)
1. pin #9 = pin #17(internally connected). 2. Do not tie up Vp and VDD : Vp is the source of digital noises. The power for analog part is supplied by VDD. If Vp and VDD are tied together, noisy Vp corrupts the power source for the analog part.
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
PIN DESCRIPTION
Pin No 1 Symbol VDD1 I/O Description
KB8821/22/23
Power supply voltage input for the RF PLL part. V DD1 must equal VDD2. In order to reject supply noise, bypass capacitors must be placed as close as possible to this pin and be connected directly to the ground plane. Power supply voltage input for RF charge pump(≥ VDD1). Internal RF charge pump output for connection to an external loop filter whose filtered output drives an external VCO. Ground for RF digital blocks. RF prescaler input. The signal comes from the external VCO. The complementary input of the RF prescaler. A bypass capacitor must be placed as close as possible to this pin and be connected directly to the ground plane. The bypass capacitor is optional with some loss of sensitivity. Ground for RF analog blocks. Reference counter input. TCXO is connected via a coupling capacitor. Ground for IF digital blocks. Multiplexed output of the RF/IF programmable counters, the reference counters, the lock detect signals and the shift registers. The output level is CMOS level. (see fout Programmable Truth Table) CMOS clock input. Serial data for the various counters is transfered into the 22-bit shift register on the rising edge of the clock signal. Binary serial data input. The MSB of CMOS input data is entered first. The control bits are on the last two bits. CMOS input. Load enable CMOS input. When LE becomes high, the data in the shift register is loaded into one of the four latches(by the control bits). Ground for IF analog blocks. The complementary input of the IF prescaler. A bypass capacitor must be placed as close as possible to this pin and be connected directly to the ground plane. The bypass capacitor is optional with some loss of sensitivity. IF prescaler .