Document
Ordering number : EN5279B
CMOS LSI
LC4100C
LCD Dot Matrix Common Driver for STN Displays
Overview
The LC4100C is a common driver for large-scale dot matrix LCD panels. It includes a 240-bit bidirectional shift register and 4-level LCD driver circuits. The number of bits can be further increased by using the provided input and output pins to connect multiple LC4100Cs in cascade. The LC4100C and LC4101C form a large-screen LCD panel driver chip set.
Features
• • • • • • • • • • Fabricated in a CMOS (P-sub) high-voltage process. LCD drive voltage: 36 V Logic system power-supply voltage: 3.0 to 5.5 V fload max: 1 MHz Slim chip (output pads are concentrated on one of the longer sides) 240 outputs (pad pitch: 70 µm) Bidirectional shift register The shift register can be split into two 120-bit registers. DISPOFF function that locks the drive voltages output to the LCD at fixed levels. Display duty: 1/160 to 1/480
Specifications
Absolute Maximum Ratings at Ta = 25°C ± 2°C, standard VSS, VEEn = VEE1 or VEE2, VSSn = VSS1 or VSS2
Parameter Symbol VDD Supply voltage VEEn VSSn VIN Input voltage V0, V1 V4 V5 Operating temperature Storage temperature Topr Tstg LOAD, L/R, DISP, DF, EIO1, EIO3, EIO4 Conditions Ratings –0.3 to +7 –0.3 to +40 –0.3 to +0.3 –0.3 to VDD + 0.3 VEE – 7 to VDD + 0.3 –0.3 to VSS + 7 –0.3 to +0.3 –20 to +75 –55 to +125 Unit V V V V V V V °C °C
Note: The voltages V1, V2, V3, V4, and V5 must obey the relationships VEEn + 0.3 ≥ V0 ≥ V1 ≥ VEE – 7, and 7 ≥ V4 ≥ V5 ≥ VSSn – 0.3. (Unit: V)
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LC4100C Allowable Operating Ranges at Ta = –20 to +75°C, standard VSS, VEEn = VEE1 or VEE2, VSSn = VSS1 or VSS2
Parameter Symbol VDD Supply voltage VEEn VSSn Input high-level voltage Input low-level voltage VIH VIL V0, V1 Input voltage V4 V5 Clock frequency VDD = 5 V ± 10% High-level clock pulse width EIO input setup time EIO input hold time Clock frequency VDD = 3 to 4.5 V High-level clock pulse width EIO input setup time EIO input hold time fload tw (ldh) tsu (ei) tho (ei) fload tw (ldh) tsu (ei) tho (ei) LOAD, L/R, DISP, DF, EIO1, EIO3, EIO4 LOAD, L/R, DISP, DF, EIO1, EIO3, EIO4 V0, V1 V4 V5 LOAD LOAD LOAD, EIO1, EIO3, EIO4 LOAD, EIO1, EIO3, EIO4 LOAD LOAD LOAD, EIO1, EIO3, EIO4 LOAD, EIO1, EIO3, EIO4 120 120 40 50 100 30 200 0.8 VDD 0 VEEn – 7 0 0 1 Conditions Ratings min 3.0 20 0 VDD 0.2 VDD VEEn VEEn + 7 typ max 5.5 36 Unit V V V V V V V V MHz ns ns ns kHz ns ns ns
Note: 1. The voltages V1, V2, V3, V4, and V5 must obey the relationships VEEn ≥ V0 ≥ V1 ≥ VEE – 7, and 7 ≥ V4 ≥ V5 ≥ VSSn. (Unit: V) 2. When turning on the power supplies, first turn on the logic system power supply and then turn on the high-voltage system power supply; alternatively, turn both on at the same time. When turning off the power supplies, first turn off the high-voltage system power supply and then tur.