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LC8904 Dataheets PDF



Part Number LC8904
Manufacturers Sanyo
Logo Sanyo
Description Digital Audio Interface Receiver
Datasheet LC8904 DatasheetLC8904 Datasheet (PDF)

Ordering number : EN*5014B CMOS LSI LC8904Q Digital Audio Interface Receiver Preliminary Overview The LC8904Q demodulates data transmitted between digital audio equipment in the EIAJ format (CP-1201) to a normal format signal synchronized with the receiving side input signal. Package Dimensions unit: mm 3156-QFP48E [LC8904Q] Features • Synchronizes with the transmitted EIAJ format signal using a built-in PLL circuit. • Modes are set up and codes are output according to commands sent over a m.

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Ordering number : EN*5014B CMOS LSI LC8904Q Digital Audio Interface Receiver Preliminary Overview The LC8904Q demodulates data transmitted between digital audio equipment in the EIAJ format (CP-1201) to a normal format signal synchronized with the receiving side input signal. Package Dimensions unit: mm 3156-QFP48E [LC8904Q] Features • Synchronizes with the transmitted EIAJ format signal using a built-in PLL circuit. • Modes are set up and codes are output according to commands sent over a microprocessor interface. — Input pin and output data format setup — Selection of digital source mode or analog source mode — 32-bit channel status output (consumer product mode 0) — 80-bit subcode Q data output (CRC check included) • Either a 384fs or a 512fs clock can be selected as the system clock. • Provides 256fs, 128fs, BCLK, and LRCK clock outputs. • Implements a CD subcode interface (CP-2401) using user bits. • Fabricated in a CMOS single-voltage power supply process • Package: QFP-48E SANYO: QIP48E • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN 73096HA (OT) No. 5014-1/20 LC8904Q Pin Assignment No. 5014-2/20 LC8904Q Block Diagram No. 5014-3/20 LC8904Q Pin Functions No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol DOUT/V EMPHA RC1 RC2 CCB/SUB DGND CLKMD CLK TEST1 TEST2 XMODE DVDD NC AVDD R AGND VIN VCO DVDD SBSY PW SFSY SBCK DGND DVDD XIN XOUT CLKOUT1 CLKOUT2 ERROR DGND SUB1 SUB2 BCLK DATAOUT LRCK LD/DQSY SRDT DO DI/SWDT CE/XLAT CL/SCLK DVDD DIN1 DIN2 DIN3 DIN4 DGND I I I I O O O O O O O O I I I I O O O O O O O I I O I I I I I I I/O O O I O I EIAJ data and validity flag output Emphasis monitor output (High: emphasis applied) CR oscillator input CR oscillator output Microprocessor interface selection input (High: CCB, low: SUB) Digital system ground Clock output switching (High: 256fs, low: 128fs) Clock switching input (High: 512fs, low: 384fs) Test pin (Must be tied low during normal operation.) Test pin (Must be tied low during normal operation.) Reset input Digital system power supply No connection Analog system power supply VCO oscillator band adjustment input Analog system ground VCO free-running frequency setting input PLL low-pass filter connection Digital system power supply CD subcode interface: block sync output CD subcode interface: data output CD subcode interface: frame sync output CD subcode interface: data read shift clock input Digital system ground Digital system power supply Crystal oscillator input Crystal oscillator output VCO and crystal oscillator clock output 256fs or 128fs clock output (selected by CLKMD) Error mute output Digital system ground Sampling frequency monitor output Sampling frequency monitor output Bit clock output Audio data output L/R clock output (High: left channel, low: right channel) Microprocessor interface: subcode Q data sync output Microprocessor interface: data output when CCB/SUB is low (3-state output) Microprocessor interface: data output when CCB/SUB is high (High-level open drain output) Microprocessor interface: data input Microprocessor interface: chip enable/latch input Microprocessor interface: clock input Digital system power supply Data input with built-in amplifier Data input with built-in amplifier Data input with built-in amplifier Data input with built-in amplifier Digital system ground Function No. 5014-4/20 LC8904Q Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Input and output voltage Operating temperature Storage temperature Symbol VDD max VI · VO Topr Tstg Conditions Ratings –0.3 to +7.0 –0.3 to VDD + 0.3 –30 to +75 –55 to +125 Unit V V °C °C Allowable Operating Ranges Parameter Supply voltage Symbol VDD Conditions min 4.5 typ 5.0 max 5.5 Unit V Electrical Characteristics DC Characteristics at Ta = –30 to +75°C, VDD = 4.5 to 5.5 V Parameter Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Output high-level voltage Output low-level voltage Current drain Input amplitude Note: 1. 2. 3. 4. 5. Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH VOL IDD VPP *1 *1 *2 *2 *3 *3 IOH = –1 µA IOL = 1 µA *4 *5 0.4 30 Conditions min 2.2 –0.3 0.7 VDD –0.3 0.8 VDD –0.3 VDD – 0.05 VSS + 0.05 45 VDD + 0.3 typ max VDD + 0.3 +0.8 VDD + 0.3 0.3 VDD VDD + 0.3 0.2 VDD Unit V V V V V V V V mA V Input pins other than DIN1, DIN2, DIN3, DIN4, RC1, and XMODE. TTL compatible. The XIN pin. CMOS compatible. The XMODE and RC1 pins. CMOS Schmitt compatible. VDD = 5.0 V, Ta = 25°C, and input data with an fs of 48 kHz. Conditions prior to the capacitances of the DIN1, DIN2, DIN3, and DIN4 pins. No. 5014-5/20 LC8904Q AC.


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