LC89962M

Ordering number : EN*5420 CMOS LSI LC89962, LC89962M NTSC Format Delay Line Overview The LC89962 and LC89962M are delay line circuits that provide a delayed signal by a 1H period of NTSC format with an external low-pass filter. Package Dimensions unit: mm 3001B-DIP8 [LC89962] Features Requires only the input of a 3.58-MHz clock to produce a 1H delayed signal and the external low-pass filter. Uses a 5-V single-voltage power supply. Requires a minimal number of external components due to the peripheral components provided on chip. Output signal has the same phase as the input signal. Operation has a 4fsc clock synchronized with the input clock allows these products to be used as wide bandwidth delay lines. A 4fsc clock can be output from the 4FSC pin (pin 7). Functions 906-bit CCD shift register Timing generator and CCD driver circuits Auto-bias circuit Sync-tip clamp circuit Sample-and-hold and output amplifier circuits 4 × PLL circuit 4fsc output circuit unit: mm 3032B-MFP8 [LC89962M] SANYO: DIP8 Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD LC89962 Pd max Topr Tstg LC89962M Conditions SANYO: MFP8 Ratings –0.3 to +6.0 400 140 –10 to +60 –55 to +125 Unit V mW mW °C °C SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 93096HA (OT) No. 5420-1/6 L...