Document
Ordering number : EN*5391
NMOS + CCD
LC89975M
PAL-Format Delay Line
Preliminary Overview
The LC89975M is a lower-cost PAL-Format CCD delay line based on the LC89970M, with the sizes of chip and package miniaturized and the external parts count reduced. • • • • • • • Auto-bias circuit Sync tip clamping circuit (luminance signal) Center bias circuit (chrominance signal) Sample-and-hold circuit PLL 3× circuit 3·fsc clock output circuit RD voltage generation step-up circuit
Features
• 5 V single-voltage power supply • On-chip 3× PLL circuit for 3·fsc operation from an fsc (4.43 MHz) input • Supports PAL/GBI and 4.43 NTSC systems, selected by a control pin input • Includes an on-chip comb filter for chrominance signal crosstalk exclusion. This adjustment-free circuit provides high-precision comb characteristics. • Peripheral circuits included on chip to allow operation with minimal external circuits. • Positive-phase signal input, positive phase signal output (luminance signal)
Package Dimensions
unit: mm 3111-MFP14S
[LC89975M]
Functions
• CCD shift register (for chrominance and luminance signals) • CCD drive circuit • Circuit for switching the number of CCD stages • CCD signal addition circuit
SANYO: MFP14S
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter Supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD Pdmax Topr Tstg Conditions Ratings –0.3 to +6.0 250 –10 to +60 –55 to +150 Unit V mW °C °C
Recommended Conditions at Ta = 25°C
Parameter Supply voltage Clock input amplitude Clock frequency Chrominance signal input amplitude Luminance signal input amplitude Symbol VDD VCLK FCLK VIN-C VIN-Y Sine wave Conditions min 4.75 300 — — — typ 5.00 500 4.43361875 350 400 max 5.25 1000 — 500 572 Unit V mVp-p MHz mVp-p mVp-p
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
41596HA (OT) No. 5391-1/7
LC89975M Pin Assignment
Block Diagram
No. 5391-2/7
LC89975M Control Pin
CONT Low High Mode (typical example) PAL/GBI 4.43 NTSC Chrominance signal delay (number of CCD stages) 2H (1705) + 0H (2.5) 1H (847) + 0H (2.5) Luminance signal delay (number of CCD stages) 1H (849) 1H (843)
Switching levels
Low/High Low High Symbol VL VH min –0.3 2.0 typ 0.0 5.0 max +0.5 6.0 Unit V V
Note: Since a pull-down resistor of about 70 kΩ is built in the control pin circuit, it will remain fixed at the low level if left open. 3fsc Pin This pin outputs the 3·fsc clock signal generated by the PLL 3× circuit.
Electrical Characteristics at VDD = 5.0 V, Ta = 25°C, FCLK = 4.43361875 MHz, VCLK = 500 mVp-p
Parameter Symbol IDD-1 IDD-2 Test conditions Switch states SW1 a b SW2 a a SW3 b b min typ max Unit
Power-supply current
1
27
32
37
mA
No. 5391-3/7
LC89975M Chrominance System Characteristics (with no signal applied to the Y-IN pin)
Parameter Symbol VINC-1 VINC-2 VOUTC-1 VOUTC-2 GVC-1 GVC-2 CD-1 CD-2 LNC-1 LNC-2 LCK3C-1 LCK3C-2 LCK1C-1 LCK1C-2 NC-1 NC-2 ZOC-1 ZOC-2 TDC-1 TDC-2 7 6 3 2 Test conditions Switch states SW1 a b a b a b a b a b a b a b a b a b a b SW2 a a a a a a a a a a a a a a a a a a a a SW3 b b b b b b b b b b b b b b b b a, b a, b b b min typ max Unit
Pin voltage (input)
2.2
2.7
3.2
V
Pin voltage (output)
1.5
2.0
2.5
V
Voltage gain
0
2
4
dB
Comb depth
4
—
–40
–35
dB
Linearity
5
–0.3
0.0
+0.3
dB
Clock leakage (3·fsc)
—
10
50
mVrms
Clock leakage fsc)
—
0.5
1.5
mVrms
Noise
—
0.5
2.0
mVrms Ω ns
Output impedance
8
200
350
500
0H delay time
9
—
245
—
Luminance System Characteristics (with no signals applied to the C-IN1 and C-IN2 pins)
Parameter Symbol VINY-1 VINY-2 VOUTY-1 VOUTY-2 GVY-1 GVY-2 GFY-1 GFY-2 DGY-1 DGY-2 DPY-1 DPY-2 LSY-1 LSY-2 LCK3Y-1 LCK3Y-2 LCK1Y-1 LCK1Y-2 NY-1 NY-2 ZOY-1 ZOY-2 TDY-1 TDY-2 16 15 14 13 11 10 Test conditions Switch states SW1 a b a b a b a b a b a b a b a b a b a b a b a b SW2 a a a a a a b b a a a a a a a a a a a a a a a a SW3 b b b b b b b b b b b b b b b b b b b b c, b c, b b b min typ max Unit
Pin voltage (input)
1.7
2.2
2.7
V
Pin voltage (output)
0.8
1.3
1.8
V
Voltage gain
0
2
4
dB
Frequency response
12
–2
0
2
dB
Differential gain
0
5
7
%
Differential phase
0
5
7
deg
Linearity
37
40
43
%
Clock leakage (3·fsc)
—
10
50
mVrms
Clock leakage (fsc)
—
0.5
1.5
mVrms
Noise
—
0.5
2.0
mVrms Ω µs
Output impedance
17
250 — —
400 63.88 63.43
550 — —
Delay time
18
No. 5391-4/7
LC89975M Test Conditions 1. Power-supply current with no input signal applied 2. Pin output voltage with no input signal applied (center bias voltage) 3. Measure the C-OUT output when 350-mVp-p sine wave signals are input to C-IN1 and C-IN2. GVC = 20 log C-OUT output [mVp-p] [dB] 350 [mVp-p] (PAL/GBI) (4.43 NTSC)
Measured frequencies GVC-1 4.429662 MHz GVC-2 4.425694 MHz
4. Measure the comb depth from the C-OUT output when 350-mVp-p sine wave signals of frequency fa ar.