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LMV8172 Dataheets PDF



Part Number LMV8172
Manufacturers National Semiconductor
Logo National Semiconductor
Description Vertical Deflection Output Amplifier
Datasheet LMV8172 DatasheetLMV8172 Datasheet (PDF)

LMV8172 Vertical Deflection Output Amplifier May 1997 LMV8172 Vertical Deflection Output Amplifier General Description The LMV8172 is a monolithic amplifier for driving the vertical deflection yoke of a CRT. The IC is a differential input, singleended output amplifier with a flyback generator. This architecture minimizes the power dissipation during forward scanning without slowing down the flyback. The LMV8172 is packaged in a 7-pin TO-220 power package. Features n n n n n High output curren.

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LMV8172 Vertical Deflection Output Amplifier May 1997 LMV8172 Vertical Deflection Output Amplifier General Description The LMV8172 is a monolithic amplifier for driving the vertical deflection yoke of a CRT. The IC is a differential input, singleended output amplifier with a flyback generator. This architecture minimizes the power dissipation during forward scanning without slowing down the flyback. The LMV8172 is packaged in a 7-pin TO-220 power package. Features n n n n n High output current Flyback generator Minimum external part count Works with single or dual supplies Low cross-over distortion Applications n Vertical deflection for monitors and TVs Connection Diagram DS100010-1 FIGURE 1. Top View Order Number LMV8172T See NS Package Number TA07B © 1997 National Semiconductor Corporation DS100010 www.national.com Absolute Maximum Ratings 3) (Notes 1, TC = 90˚C Thermal Resistance (θJC) Junction Temperature (TJMAX) ESD Susceptibility (Note 5) Storage Temperature Lead Temperature (Soldering 10 seconds) 20W 3˚C/W 150˚C 2 kV −65˚C to +80˚C 265˚C (Note 2) −20˚C ≤ TJ ≤ +150˚C Above 25˚C, derate based on θJC and TJ (Note 4) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage, (VS = VCC1 − VEE) Flyback Peak Voltage, (VOUT − VEE) (VCC2 − VEE) Input Voltage, (VDC) Pins 1, 7 Output Peak Current, (IO) Pin 5 (Note 8) Power Dissipation (PD) TC = 25˚C 60V 60V VEE ≤ VIN ≤ VCC1 3.2 App 41W 35V Operating Ratings Junction Temperature Range Electrical Characteristics VCC1 = +17.5V; VCC2 = +16.9V; VEE = −17.5V; TC = 25˚C unless otherwise specified. Symbol I2+6 I1 Ios V3L V5L V5H Parameter Total Quiescent Current (I2 + I6) Input Bias Current Input Offset Current Pin 3 Saturation Voltage to VEE Output Saturation Voltage to VEE Output Saturation Voltage to VCC2 See Figure 3, I3 = 20 mA See Figure 3, I5 = 1.2A I5 = 0.7A See Figure 4, I5 = −1.2A I5 = −0.7A Conditions See Figure 2 Typical (Note 6) 11 -0.5 0.5 1.1 1.3 0.7 2.6 2.1 Limit (Note 7) 20 -2.0 3.0 2.0 2.5 1.4 3.3 2.8 Units mA (max) µA (max) µA (max) V (max) V (max) V (max) V (max) V (max) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 3: All voltages are measured with respect to GND, unless otherwise specified. Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJC and the case temperature, TC. The maximum allowable power dissipation at any elevated temperature is PD = (TJMAX − TC) / θJC or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJMAX = 150˚C. The typical thermal resistance (θJC) of the LMV8172 is 3˚C/W. Note 5: Human Body model, 100 pF capacitor discharged through a 1.5 kΩ resistor. Note 6: Typicals are at TC = 25˚C and represent most likely parametric norm. Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: Maximum output current is tested with a load of 3 mH, VCC1 = +15V and VEE = −15V, VIN+ set so the device is drawing equal amounts of current from both supplies, and the sawtooth on VIN− set so the voltage waveform on pin 5 is as large as possible without distortion. www.national.com 2 Test Circuits DS100010-2 FIGURE 2. DS100010-3 FIGURE 3. 3 www.national.com Test Circuits (Continued) DS100010-4 FIGURE 4. Block Diagram DS100010-5 FIGURE 5. Application Hints To get the best possible performance from the LMV8172T it is important to use a good PCB layout and the correct components. The 0.1 µF and 470 µF capacitors on the VCC1 and VEE lines should be as close as possible to their pins. The power traces should be wide and there should be no jumpers between the capacitors and the LMV8172T. The value of the electrolytic capacitors used on the VCC1 and VEE lines should be 470 µF or greater. The ground traces should also be as wide as possible. The diode and optional capacitor should be located close to the LMV8172T. The diode should be a fast-recovery type, the 1N4937 recommended has a trr of 150 ns. The capacitor is optional, it may be needed in some PCB layouts. A suggested layout is shown in Figure 6. www.national.com 4 Application Hints (Continued) DS100010-6 FIGURE 6. Typical Application DS100010-7 FIGURE 7. 5 www.national.com LMV8172 Vertical Deflection Output Amplifier Physical Dimensions inches (millimeters) unless otherwise noted Order Number LMV8172T NS Package Number TA07B LIFE SUPPORT POLICY NATIONAL.


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