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PEEL18CV8PI-5 Dataheets PDF



Part Number PEEL18CV8PI-5
Manufacturers ETC
Logo ETC
Description CMOS Programmable Electrically Erasable Logic Device
Datasheet PEEL18CV8PI-5 DatasheetPEEL18CV8PI-5 Datasheet (PDF)

® International CMOS Technology Commercial/ Industrial PEEL™ 18CV8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device Features s Multiple Speed Power, Temperature Options - VCC = 5 Volts ±10% - Speeds ranging from 5ns to 25 ns - Power as low as 37mA at 25MHz - Commercial and industrial versions available CMOS Electrically Erasable Technology - Superior factory testing - Reprogrammable in plastic package - Reduces retrofit and development costs Development / Programmer Sup.

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® International CMOS Technology Commercial/ Industrial PEEL™ 18CV8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device Features s Multiple Speed Power, Temperature Options - VCC = 5 Volts ±10% - Speeds ranging from 5ns to 25 ns - Power as low as 37mA at 25MHz - Commercial and industrial versions available CMOS Electrically Erasable Technology - Superior factory testing - Reprogrammable in plastic package - Reduces retrofit and development costs Development / Programmer Support - Third party software and programmers - ICT PLACE Development Software and PDS-3 programmer - PLD-to-PEEL JEDEC file translator s Architectural Flexibility - Enhanced architecture fits in more logic - 74 product terms x 36 input AND array - 10 inputs and 8 I/O pins - 12 possible macrocell configurations - Asynchronous clear - Independent output enables -- 20 Pin DIP/SOIC/TSSOP and PLCC s s Application Versatility - Replaces random logic - Super sets PLDs (PAL, GAL, EPLD) - Enhanced Architecture fits more logic than ordinary PLDs General Description The PEEL18CV8 is a Programmable Electrically Erasable Logic (PEEL) device providing an attractive alternative to ordinary PLDs. The PEEL18CV8 offers the performance, flexibility, ease of design and production practicality needed by logic designers today. The PEEL18CV8 is available in 20-pin DIP, PLCC, SOIC and TSSOP packages with speeds ranging from 5ns to 25ns with power consumption as low as 37mA. EE-Reprogrammability provides the convenience of instant reprogramming for development and reusable production inventory minimizing the impact of programming changes or errors. EE-Reprogrammability also improves factory testability, thus assuring the highest quality possible. The PEEL18CV8 architecture allows it to replace over 20 standard 20-pin PLDs (PAL, GAL, EPLD etc.). It also provides additional architecture features so more logic can be put into every design. ICT’s JEDEC file translator instantly converts to the PEEL18CV8 existing 20-pin PLDs without the need to rework the existing design. Development and programming support for the PEEL18CV8 is provided by popular third-party programmers and development software. ICT also offers free PLACE development software and a low-cost development system (PDS-3). Figure 1 Pin Configuration I/CLK I I I I I I I I GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC I/O I/O I/O I/O I/O I/O I/O I/O I Figure 2 Block Diagram DIP TSSOP PLCC SOIC 1 04-02-004H ® International CMOS Technology PEELTM 18CV8 Figure 3 PEEL18CV8 Logic Array Diagram 2 04-02-004H ® International CMOS Technology PEELTM 18CV8 array. (Note that PEEL device programmers automatically program all of the connections on unused product terms so that they will have no effect on the output function). Function Description The PEEL18CV8 implements logic functions as sum-ofproducts expressions in a programmable-AND/fixed-OR logic array. User-defined functions are created by programming the connections of input signals into the array. Userconfigurable output structures in the form of I/O macrocells further increase logic flexibility. Programmable I/O Macrocell The unique twelve-configuration output macrocell provides complete control over the architecture of each output. The ability to configure each output independently permits users to tailor the configuration of the PEEL18CV8 to the precise requirements of their designs. Architecture Overview The PEEL18CV8 architecture is illustrated in the block diagram of Figure 2. Ten dedicated inputs and 8 I/Os provide up to 18 inputs and 8 outputs for creation of logic functions. At the core of the device is a programmable electricallyerasable AND array which drives a fixed OR array. With this structure, the PEEL18CV8 can implement up to 8 sumof-products logic expressions. Associated with each of the 8 OR functions is an I/O macrocell which can be independently programmed to one of 12 different configurations. The programmable macrocells allow each I/O to create sequential or combinatorial logic functions of active-high or active-low polarity, while providing three different feedback paths into the AND array. Macrocell Architecture Each I/O macrocell, as shown in Figure 4, consists of a Dtype flip-flop and two signal-select multiplexers. The configuration of each macrocell is determined by the four EEPROM bits controlling these multiplexers. These bits determine output polarity, output type (registered or nonregistered) and input-feedback path (bidirectional I/O, combinatorial feedback). Refer to Table 1 for details. Equivalent circuits for the twelve macrocell configurations are illustrated in Figure 5. In addition to emulating the four PAL-type output structures (configurations 3,4,9, and 10), the macrocell provides eight additional configurations. When creating a PEEL device design, the desired macrocell configuration generally is specified explicitly in the design file. When the design is assembled.


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