MC100E175

www.DataSheet4U.com MC10E175, MC100E175 5V ECL 9-Bit Latch With Parity Description The MC10E/100E175 is a 9-bit latch. It also features a tenth latched output, ODDPAR, which is formed as the odd parity of the nine data inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH). The E175 can also be used to generate byte parity by using D8 as the parity-type select (L = even parity, H = odd parity), and using ODDPAR as the byte parity output. The LEN pin latches the data when asserted with a logical high and makes the latch transparent when placed at a logic low level. Features http://onsemi.com 9-Bit Latch Parity Detection/Generation 800 ps Max. D to Output Reset PECL Mode Operating Range: VCC = 4.2 V to 5.5 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.5 V Internal Input 50 kW Pulldown Resistors ESD Protection: Human Body Model; > 2 kV, Machine Model; > 200 V Charged Device MOdel; > 2 kV Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level: Pb = 1 Pb−Free = 3 For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 416 devices Pb−Free Packages are Available* PLCC−28 FN SUFFIX CASE 776 MARKING DIAGRAM* 1 MCxxxE175FNG AWLYYWW xxx A WL YY WW G = 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND80...